Products Mentioned

AD9361 Recommended for New Designs
The AD9361 is a high performance, highly integrated radio frequency (RF) Agile Transceiverâ„¢ designed for use in 3G and 4G base station applications....
AD9361 on Analog.com

Thread Details

  • State Not Answered
  • Replies 5 replies
  • Subscribers 51 subscribers
  • Views 187 views
  • Users 0 members are here
Options
 
Related Content

        

            Post
             Go back to editing
        

    

    


    

    









		


















	
	
			
	
			
		
	
	
		

	    
	    
	    		
Frequency offset between input clock and generated signal on FMCOMMS3

		
	
				

			

									
					    roblkc3
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Oct 30, 2025 
				
			
			
		
    
		
		                     
				
        		
    
		    
		    		    
    
		      		            		        
    Category: Hardware
    
    		        		        		    		    
    
		    		    
		    			
    
			    
    Hello,
    

    I am developing a system that uses as a prototype a ZCU105 with a FMCOMMS3 daughterboard. For my application, I need the generated carrier to be frequency-locked to the reference clock fed into the FMCOMMS3.
    If I take an Ettus B210 board and feed it an external 10 MHz reference, I can observe on the oscilloscope that a sinusoid with a 2.45 GHz carrier and the 10 MHz input are perfectly locked in frequency. However, this does not seem to be the case with my FMCOMMS3 setup.
    I first noticed this issue when transmitting a sinusoid at a frequency exactly equal to one quarter of the sampling rate (i.e., 4 IQ points per period when I sample it) from one FMCOMMS3 and receiving it on another. In a wired loopback (not digital), I observe four point clusters --- somewhat messy, but fixed in position. However, when using two boards with an external 40 MHz reference clock, I see a big circle.
    Again, the same test with two B210 boards gives four (significantly smaller) point clouds.
    Interestingly, if I reduce the carrier frequency from 2.45 GHz to 245 MHz, the FMCOMMS3 constellation again shows four large, somewhat distorted point clusters instead of a circle.
    

    What am I missing?
    

    Thanks a lot in advance!
    

    Best regards,
    Rob
    
			
    
			
									
		                             
                        

    
    
                                            
                 hardware
                
                                                    
                 ad9361
                
                                                    
                 Wideband Transceiver IC
                
                                                    
                 ad9361 configuration
                
                                                    
                 RF Integrated Transceivers
                
                                
            
    
    
    
		
    

				
				        
        		
    
			
						
									
												
			
			
                        
                                    
                        
                        
                        
            
			            
						
						
			
			
			
			
		
    

        
        
        
    
					
    
			
    


    
















    
	
    
	
    
					



			


				
	









	
      
	

    • 
	
      



	
		
	
	



      
	
      
		
      
							
					
      
		
      
		    
		    		    
			
				
									
							        
			
			
			
      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Oct 30, 2025 9:46 PM
            
            
						
			            		
      
		
										0
					
	
      

		
		
      
		
      
                                
                                                            
      
					
      HI  
      

      

      Thanks for your post.
      

      It would be helpful. if you can post with spectrum plots to understand the issue clearly.
      

      

      Regards,
      

      SJ
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

      • 

	

    • 
	
      



	
		
	
	



      
	
      
		
      
							
					
      
		
      
		    
		    		    
			
				
									
							        
			
			
			
        
            
						
                            
            
            				
            
                on Oct 31, 2025 2:13 AM
            
            
												
						in reply to SJagini
					
										
			            		
        
		
										0
					
	
        

		
		
        
		
        
                                
                                                            
        
					
        Hello,
        


        Thanks for your reply!
        Here's what I plot from the retrieved data.
        

         
        

        (I have a sampling rate of 10 MHz, so the sinusoid is at 2.5 MHz).
        

        Best,
        

        Rob
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

        • 

	

      • 
	
        



	
		
	
	



        
	
        
		
        
							
					
        
		
        
		    
		    		    
			
				
									
							        
			
			
			
          
            
						
                            
            
            				
            
                on Dec 4, 2025 5:26 AM
            
            
												
						in reply to SJagini
					
										
			            		
          
		
										0
					
	
          

		
		
          
		
          
                                
                                                            
          
					
          Dear SJagini,
          

          After quite a lot of investigations, it seems that the issue derives from the jitter on the 40 MHz reference clock. We generate the 40 MHz using an FPGA which is fed with a 10 MHz reference clock, and if we pass the generated 40 MHz into an external jitter cleaner, then everything works as expected, while feeding it directly makes the 4 points corresponding to the samples sinusoid move so much that they look like a circle when acquired.
          

          My question: is there a way to configure (using the NO-OS driver) the internal PLL to compensate for the increased jitter on the reference clock?
          

          Thanks a lot for any help!
          

          Best regards,
          Rob
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

          • 

	

        • 
	
          



	
		
	
	



          
	
          
		
          
							
					
          
		
          
		    
		    		    
			
				
									
							        
			
			
			
          •  Analog Employees  
          
            
						
                            
            
            				
            
                on Dec 4, 2025 5:55 AM
            
            
												
						in reply to roblkc3
					
										
			            		
          
		
										0
					
	
          

		
		
          
		
          
                                
                                                            
          
					
          HI  
          

          

          Unfortunately, the AD9361’s internal PLL cannot compensate for reference clock jitter—it assumes a reasonably clean input. The BBPLL and RF PLLs multiply the reference frequency, so any jitter on the 40 MHz input is amplified, which explains why your constellation collapses when the reference is noisy. This explains at lower freq it works and goes worse at higher freq.
          

          

          

          AD9361 expects a reference clock with low phase noise and jitter. Jitter on the reference clock translates directly into LO phase noise and sampling clock instability, degrading EVM and SNR.
          

          

          You may have to use external jitter cleaner or clock synthesizer. alternatively, in most application they yse low-jitter reference clock like External XO or TCXO with better jitter spec.
          

          

          Regards,
          

          SJ
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

          • 

	

        • 
	
          



	
		
	
	



          
	
          
		
          
							
					
          
		
          
		    
		    		    
			
				
									
							        
			
			
			
            
            
						
                            
            
            				
            
                on Dec 5, 2025 1:22 AM
            
            
												
						in reply to SJagini
					
										
			            		
            
		
										0
					
	
            

		
		
            
		
            
                                
                                                            
            
					
            Dear SJagini,
            

            Thanks for your quick reply!
            Actually, from the latest measurements, it seems that the jitter of the "non-working clock" is better than the "working" one. So we're totally puzzled... We keep investigating but we're running out of options... Disappointed
            

            I'll keep you posted. Thanks again and have a nice week-end!
            

            Best,
            Rob
            
			
            

		
			
	      

		
		
	
            
	
            
		
            
			
		
            
	
            
	
            
		
						
						
				
						
				
				
		
		
            
			
		
            
	
            

            

            •