Spike over the Received IQ

Tagging andrei_g for support.

Hi,

To me, it seems to be an interface issue. A drift caused by temperature or something, that is affects on of the lanes charring a bit closer to the least significant part of the data.
Considering this is a spartan 7. I guess you are not using any IO delays in the FPGA.
Is the no-OS delay tunning algorithm used, that one that uses the IO delay resources from AD9361 device?

For solving this you could use constraints to change the delays on the lines or force different delays from the AD9361.
Find out which bit is the one with the glitches and start from there. You could check the the interface code from the libraryaxi_ad9361/xilinx/axi_ad9361_if.v

Andrei

Hi Stanca ,

Not yet — I’m still working on identifying the issue.

I’ve checked the PLL registers to verify that they are locking correctly, but the problem still persists. Do you have any suggestions for pinpointing the root cause or potential approaches to resolve it? I’ve also tested with a different board, but the issue remains the same.

Regards,

PADT

To conclude, no matter the input signal's attributes, you still observe the same issue?

Are you able to use another supply, to check if the behavior changes?

Hi Stanca ,

Following your question, I conducted several tests with different input signals and also evaluated the system using an alternative supply. The behavior remains unchanged.
Do you have any further suggestions that might help in resolving this issue?

Regards,

PADT

Hi,

Sorry for the delay reply, I've missed our post.
I'm out ideas...
From the test I suggested I believe the issue is somewhere between the RF frontend and the digital interface.
The digital interfaces itself was validated with the loopback.
Could be a device configuration.
I'm moving this thread to the Design support AD9361 forum, hoping someone here can help you.

Andrei

Hi ParasADT andrei_g 

Pls correct me if i understood correctly from the whole thread that Rx ADC Data has intermittent glitches.

Please check at full scale RX input from BIST tone or external signal input if you observe the amplitude beyond Rx amplitude full scale then it is conversion issue of LVDS Data to ADC amplitude in the signal data. 

And the other one is about LVDS data timing issue with FPGA. Pls try with very lower sampling rate to figure out.

Regards,

SJ

Hi SJagini , andrei_g 

I completed the tests as described. When the BIST tone is injected directly into the RX path at any amplitude, the received signal remains clean with no observable spikes. This behavior is consistent across sample rates from 0.96 MSPS to 15.36 MSPS.

However, when an RF-level input signal is applied, the spikes reappear.

Across the full signal chain, these spikes are not persistent—they occur intermittently. After a few power cycles, they may either reappear or temporarily disappear.
For additional details, please refer to the earlier section of the thread.

Regards,

PADT

HI ParasADT 

Appreciate your efforts on checking with BIST.

Pls check the FFT plot of the data. Also, it may be possibility of cross coupling of other components in the board. Pls try with some shielding on RF tracks. As this is at 200KHz looks like coming from power supply or inductor to RF chain.

Regards,

SJ

Hi SJagini ,

I attempted to isolate the power source by replacing it with the ADI PMIC provided by the regional team, as well as by using an external power supply. However, the issue still persists. I also implemented RF shielding on the RF tracks, but no improvement was observed and the issue remains.

Regards,

PADT

HI ParasADT 

Just to ensure that, what is the switching Freq applied in the power supply.?

Pls change the Freq and see the behavior.

Does the spike Freq changing with power supply ?

if you terminate the Rx port with 50ohm and then also are you observing any spikes in Rx Data.?

Regards,

SJ

Hi SJagini ,

When I terminate the Rx port with 50 Ω, I still observe spikes in the received data.

Regarding the power-supply switching frequency, I was advised to use the MAX77511, whose nominal switching frequency is approximately 1 MHz.

I also evaluated a different PMIC and varied its switching frequency. However, I continue to observe the same spikes, with no change in the spike occurrence frequency, even after modifying the power-supply switching frequency.

Please let me know if further measurements or checks are required.

Regards,

PADT

Hi SJagini ,

When I terminate the Rx port with 50 Ω, I still observe spikes in the received data.

Regarding the power-supply switching frequency, I was advised to use the MAX77511, whose nominal switching frequency is approximately 1 MHz.

I also evaluated a different PMIC and varied its switching frequency. However, I continue to observe the same spikes, with no change in the spike occurrence frequency, even after modifying the power-supply switching frequency.

Please let me know if further measurements or checks are required.

Regards,

PADT