Spike over the Received IQ

Doesn't look like a software issue, perhaps the HDL team can help you, I've moved the thread in the relevant subforum.

Tagging andrei_g for support.

Hi,

To me, it seems to be an interface issue. A drift caused by temperature or something, that is affects on of the lanes charring a bit closer to the least significant part of the data.
Considering this is a spartan 7. I guess you are not using any IO delays in the FPGA.
Is the no-OS delay tunning algorithm used, that one that uses the IO delay resources from AD9361 device?

For solving this you could use constraints to change the delays on the lines or force different delays from the AD9361.
Find out which bit is the one with the glitches and start from there. You could check the the interface code from the libraryaxi_ad9361/xilinx/axi_ad9361_if.v

Andrei

Hi andrei_g ,

Yes , As you Said , No IO Delays are configured , all those Delays are kept as 0.I will Experiment By using Different Delays , and get back to you , But as far as I observed , We can not tell that , specific Bit is getting Glitch.

Regards,

PADT_Blr

Hi ParasADT ,

Have you had the opportunity to test the proposed suggestions?

Regards, Elena

Use dac adc valid for ila clock or set clock same as the sampling rate 

Hi elenahadarau ,

I attempted modifying the parameters delay_rx_data , rx_data_clock_delay , rx_data_delay , tx_fb_clock_delay , and tx_data_delay on the NO-OS side. In addition, I tested the setup across multiple power cycles.

However, I observed that the spike issue still persists. For certain delay settings, the spikes appear consistently, while for others, they tend to reoccur after a few power cycles (typically within 2–3).

Regards,

PADT

Hi,

Have you found the issue? If not here's another idea.

There should be a loopback option. Loopback between Tx and Rx inside AD9361, That way that you send will be received, maybe the problem is somewhere else not on the digital interfaces. Some noise affecting the clock path.

Andrei

Hi andrei_g , 

The setup was tested by transmitting the BIST tone signal from the AD9361 to the FPGA, during which no spikes were observed. Similarly, no spikes were detected during testing with the AD9364 Data Loopback. However, spikes were observed only during RF-level signal testing. I am still trying to find the root cause of this issue .

Regards,

PADT

I would look in the FFT domain.
Maybe that noise is an image of a crosstalk with a clock affecting the end LO, from a power supply or something.

Andrei