Customize AD9361 IQ Phase

I'm taggingtravisfcollins for support.

Thanks,

Are you using Linux or no-Os drivers for configuring the chip? Are you using eval board or custom board? Also, what is the FPGA that you use? 

I'm using no-os and i connected signal's directly to ad9361_adc and dac FIFO IP.

By board is Puzhi eval board SDR_201_PRO with Zynq 7020.

Phase deference between i and q is random and when I programing the board , sometimes phase deference in 0 and sometimes is 180 and 180 is like my signal shape like dac picture.

Also my i signal is completely in positive level and q signal in negative level, like the DAC picture. But when i disabled bbdc_offset, iq swipe and is random too

Can you share the I and Q plot of the data that you are generating from your custom block?

Also, can you try sending data into the RX digital interface using BIST and then capture and check the data at the RX output? Refer to the below link:

 AD936x Built in Self Test (BIST)  

Thank you for answering 

I shared the picture that you mentioned before. First picture named DAC is generated by my ip

And also i tested with BIST, and it was ok and i could see that my signals are loop back completely correct.

As you can see that the I and Q signals that are sent by your IP are 180 degree out if phase, which is not correct. You need to generate the I and Q  signals with 90 degree phase difference.

If BIST is correct then there is no issue in the AD9361 hardware.

I don't understand what you mean.

I need to send the first waveform that says dac on it and receive the same. But sometimes I get the waveform right from the receiver, meaning the difference is the same as what I send, but sometimes the waveform I receive has no phase difference and the iq signals are not reversed and are the same as each other. Also when I use bist instead of rf loop, I get exactly what I send, but when it passes through rf, the received phase difference is corrupted.

So you are deliberately sending the I and Q signals out of phase by 180 degree. The phase ambiguity of zero or 180 degree while involving the RF path is expected and occurs due to the dividers. Refer to the below links:

 RE: Phase Difference in AD9361 Multichip Synchronization 

 Phase ambiguity caused by VCO divider   .  

Thank you for your help. I figured out the problem. I don't need to send exactly the same waveform and I achieved my goal by making some changes in the receiver module of my hood. I have another question for you, is it possible to make a setting so that the received i signal is always above zero and positive? That is, all signal values are converted to positive values with a shift?