ad9363 tune delay fail but rx ok

I notice zedboard and fscomm2 use 2.5V vdd .

would 1.8V vdd work??

I monitor I/Q chanel and enanble,valid 

the result loos fine.

So I guess this is the hardware Problem. So I check the fbclk,and txframe signal from scope

the Common Mode Voltage is 0.9v,the nitor I/Q chanel and enanble,valid 



the result loos fine.



So I guess this is the hardware Problem. So I check the fbclk,and txframe signal from scope，differential mode voltage is 400mv

I think this meet the requirements for ad9361.

the supply voltage of ad9361's digtaltal interface is 1.8V

so please any suggestion.



the Common Mode Voltage is 0.9v,the 

How are you switching between CMOS and LVDS interface continuously in your design? What is the sample rate, when you are switching to LVDS mode? If the interface tuning is not running, then there is an issue with the interface and check for  Signal integrity issues on the lanes connecting between AD9363 and FPGA. 

Refer to the below supported VDD INTERFACE levels in CMOS and LVDS mode.

problem sloved. lvds tx  data pin inverted and pin location is wrong. thanks for your reply.