Harmonics over the BIST

You should be able to reduce the spur levels by optimizing the power supply . If the bandwidth requirement is small , you can reduce the filter bandwidth and get some rejection for the spur. 

The harmonics seen looks to be because of Tx path saturation , Can you reduce the power going into Tx and check ? 

Hi Vinod ,

Here , I am  sending the BIST signal From AD9364 , at the amplitude of Fs/2 , by making 0X3F4 register {D5:D4} as "01" , as mentioned in the datasheet to FPGA , and from the  FPGA , Im just looping back(Sending back , all the data im receiving from AD9364) , so On FPGA , i don't have any control over the amplitude and power level of the BIST signal back to the TX of AD9364. .
                                                    

Also , if the Power level (Amplitude) is the one of the factor , when i feed the BIST signal directly to TX of AD9364 ,can i know  why the spectrum looks bit clean , without much spurs/harmonics , as in the previous message in this thread.?

I am sharing AD9364 Filter Wizard configuration , with you below, can you help me in configuring for better output ?

Regards,

Paras ADT-Blr Team

You can check the interface tuning , its part of the drivers . So you should be doing this already . 

wiki.analog.com/.../interface_timing_validation

Do you see similar issue of the Rx side as well.? 

If you are sending tone from FPGA , can you try reducing the tone power by 6dB (-6dBFS) or 9dB , to ensure that Tx DAC is not getting saturated.

Hi Vinod ,

I am not performing Interface Timing Validation as this process is associated with the AD9361_Conv file, which requires AXI files. Given that our architecture does not incorporate AXI files, we have excluded this testing. However, we have conducted BIST testing and Data Loopback.

Additionally, regarding the tone signal, I am currently transmitting data at a power level of -10 dB.

Regards,

Paras ADT BLR Team

The issue that you are seeing could be because of any of the below ,

• Power supply going below the tolerance limit during initialization. Balun supply being noisy. 
• Interface timing issue : Manually tune the data clk delay (reg 0x006) 
• Noisy reference clock. 
• wrong sampling rate for the input signal

Without sending any signal how is the Tx output noise floor. ?

If the input tone power is -10dBFs , DAC saturation can be ruled out. 

Hi Vinod ,

• Could you please explain how manually tuning the DataClk delay can result in a better spectrum?

• Is there any relationship between the sampling rate within the FPGA and the sampling rate inside the AD9364? Additionally,

  "wrong sampling rate for the input signal" Represents?

• Tx Noise floor , without sending any signal looks as below

Regards,

Paras ADT BLR Team

Without input signal, spectrum noise floor looks good. You can try sending tone at different power levels (say -40dBFS, -30 ,-20 etc) and check when the noise floor starts to degrade. 

On sampling rate , its the rate at which you are sending data from FPGA and that should be same as the input FIR clock. 

In below example the sampling rate is 61.44 MHz, I guess your case its 30.72 MHz. 

    {983040000,245760000,122880000,61440000,61440000,61440000}, // tx_path_clks[6]

FYR  RE: Sampling frequency in fmcomms3-ebz 

Hi Vinod ,

1) Yes, we are fixing the FIR clock and the rate at which FPGA is sending the data is same.

2)Consider , if my TX_path_Clks are set set as below ,

{983040000,245760000,122880000,61440000,30720000,7680000}, // tx_path_clks[6]

Now , the sampling rate inside AD9364 will be 30.72  ,But the sampling rate inside FPGA , we have set is 7.68 , which is also the FIR input clock rate.Is this sampling configuration at both the ends that we are following is fine ?

3) I tested TX noise floor ,by transmitting a constant signal of 0x7FF and observed the spectrum for the span of 100 KHz  as below, which is pretty clean as compared to sine wave .

However, when I transmit a sine wave, it remains unchanged. Upon examining the noise floor by varying the attenuation rate, I observe that the noise floor also attenuates as we adjust the attenuation factor. Unfortunately, the main signal also experiences an equivalent level of attenuation.

Could you provide some insights on identifying the issue and mitigating the spurious distortions observed in the sine wave? I have attached the transmission spectrum result at 456 KHz below, where I observe peaks at the local oscillator (LO) frequency, as well as at +456 KHz and -456 KHz, accompanied by significant disturbances.

Regards,

PARAS ADT_BLR_Team

What is the difference in the tone signal between the above two screen captures,? How are you generating sine wave? So looks like your configuration is correct and issue is with the waveform.

Mark23 said:

Now , the sampling rate inside AD9364 will be 30.72  ,But the sampling rate inside FPGA , we have set is 7.68 , which is also the FIR input clock rate.Is this sampling configuration at both the ends that we are following is fine ?

The sampling rate in above example is 30.72 MHz. So from what you shared your sampling rate is 7.68 and matches with FPGA rate , If i understand correctly

{983040000,245760000,122880000,61440000,30720000,7680000}, // tx_path_clks[6]

Hi Vinod ,

1st Screen capture that you are seeing above is just a constant signal 0x7FF ,Whereas 2nd Screen capture reprsents a sine wave  of 456 KHz , which is being generated in MATLAB , and I'm feeding the IQ values to Block RAM in vivado and pushing it to LVDS.

Regards,

PARAS ADT_BLR Team

Are you upsampling the sinewave at 456KHz to 7.68 MHz in FPGA before sending over the interface to AD9361 ? You need to do that. 

Hi Vinod ,

Yes, i am sampling the sine wave at MATLAB itself and creating the IQ samples, then only im feeding into Block RAM.

Regrads,

PARAS ADT_BLR Team

Hi Vinod ,

Yes, i am sampling the sine wave at MATLAB itself and creating the IQ samples, then only im feeding into Block RAM.

Regrads,

PARAS ADT_BLR Team

I suspect the waveform here as issue is seen only on second capture only , try with another modulated waveform.

Mark23 said:

1st Screen capture that you are seeing above is just a constant signal 0x7FF ,Whereas 2nd Screen capture reprsents a sine

First capture , how are you generating the constant signal. ? Isn't that a sine tone ? 

Hi Vinod ,

I tried to send  other waveforms, but results remains the same.And Regarding Constant Signal , I am directly feeding it to the LVDS lines , same way how im feeding the Modulated IQ's, as per the AD9364 Requirements.

If Waveform  is the issue , how to verify that apart from feeding it directly into IIO Oscilloscope,when we try to feed in IIO Oscilloscope , our eval board is getting very heated , and IIO scope is getting struck.

Regards,

PARAS ADT_BLR Team

Can you try with the default available waveforms, to rule out the waveform issue? Also, note that AD9361 bus width is 12 bits. So, you need to format the data file, accordingly .Refer to the below link:

https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/basic_iq_datafiles