Harmonics over the BIST

You should be able to reduce the spur levels by optimizing the power supply . If the bandwidth requirement is small , you can reduce the filter bandwidth and get some rejection for the spur. 

The harmonics seen looks to be because of Tx path saturation , Can you reduce the power going into Tx and check ? 

Hi Vinod ,

Here , I am  sending the BIST signal From AD9364 , at the amplitude of Fs/2 , by making 0X3F4 register {D5:D4} as "01" , as mentioned in the datasheet to FPGA , and from the  FPGA , Im just looping back(Sending back , all the data im receiving from AD9364) , so On FPGA , i don't have any control over the amplitude and power level of the BIST signal back to the TX of AD9364. .
                                                    

Also , if the Power level (Amplitude) is the one of the factor , when i feed the BIST signal directly to TX of AD9364 ,can i know  why the spectrum looks bit clean , without much spurs/harmonics , as in the previous message in this thread.?

I am sharing AD9364 Filter Wizard configuration , with you below, can you help me in configuring for better output ?

Regards,

Paras ADT-Blr Team

If the digital signal to DAC is close to 0dBFS , you will see DAC harmonics.  Typically modulated waveforms are used and the average signal power levels are around -10 dBFs , (depending on PAR of the signal) BIST signals are for checking the functioning of data path and may not be good to analyze performance. 

You can continue your tests using actual signal or CW signal from FPGA. When using CW send with a power of -6dBFS or lower.  

HI Vinod ,

We tested witha  CW tone signal of 460 KHz signal  at the LO of 450 MHz, at the rate of the sampling rate 7.68 MHz , with the amplitude of 0-1024 , and attenuation 10 dB, with the filter as mentioned above (from AD9364 filter Wizard), and when i programmed for the first time , i got as below .

with a DC offset at 450 MHz , and i got two signals , both are spaced around 460 KHz from LO.Now  , We are working to Reduce DC from our end signal generation , but how to suppress the other signal (harmonic).

But also, when i program AD9364 with the same code again from FPGA , the spectrum becomes as below, and persists same , even if i try to program many times, as below.

So , only at certain times , the spectrum lookssomewhat  clean (randomly) , at all other times the spectrum looks as like  2nd image.Which is causing this issue?Can i have some insights about it .

Regards,

Paras_ADT BLR Team

Hi Vinod ,

Can i have the update over this ?

Regards,

Paras_ADT BLR Team

Your LO is at 450 MHz, Center of the plot (marker 1 of second plot),are you sending tone at +460 KHz or -460 KHz ? In any case if right side one is your tone , what you see on left side is the image. 

Are you running Tx quad cal ? Typically quad cal should suppress LO leakage and image to less than 50 dBc. 

The noise floor in these plots seems to be very high compared to the first plot shared. Are you using FIR or you are in FIR bypass mode.? 

Your filter is having passband of 500 KHz with 30.72 MSPS sampling rate , Is my understanding correct. Try plotting the filter response in FVtool and cross check. 

If the issue is random , check the 1.3V power supply to the Tx_A_N amd Tx_A_N_P pins via Tx balun. (alternate option is to feed via inductors). If this voltage is low or has noise that impacts output spectrum.

Hi Vinod ,

I would like to confirm that the local oscillator (LO) is set at 450 MHz. I am transmitting a +460 kHz signal from the FPGA to the AD9364, but I am also observing an output at -460 kHz on the spectrum analyzer.

Additionally, I am currently executing the TX Quad Calibration settings. Regarding the filter configuration, I am utilizing a filter with a passband of 500 kHz and a sampling rate of 30.72 MSPS, as previously mentioned. For your reference, I have attached the FVTool response.

Furthermore, on our custom board, I am externally connecting the 1.3 V power supply to the balun.But what else , could be the reason for that randomness.?

Thank you for your attention to this matter.

Regards,

Paras ADT BLR Team

You can check the interface tuning , its part of the drivers . So you should be doing this already . 

wiki.analog.com/.../interface_timing_validation

Do you see similar issue of the Rx side as well.? 

If you are sending tone from FPGA , can you try reducing the tone power by 6dB (-6dBFS) or 9dB , to ensure that Tx DAC is not getting saturated.

Hi Vinod ,

I am not performing Interface Timing Validation as this process is associated with the AD9361_Conv file, which requires AXI files. Given that our architecture does not incorporate AXI files, we have excluded this testing. However, we have conducted BIST testing and Data Loopback.

Additionally, regarding the tone signal, I am currently transmitting data at a power level of -10 dB.

Regards,

Paras ADT BLR Team

The issue that you are seeing could be because of any of the below ,

• Power supply going below the tolerance limit during initialization. Balun supply being noisy. 
• Interface timing issue : Manually tune the data clk delay (reg 0x006) 
• Noisy reference clock. 
• wrong sampling rate for the input signal

Without sending any signal how is the Tx output noise floor. ?

If the input tone power is -10dBFs , DAC saturation can be ruled out.