AD9361
Recommended for New Designs
The AD9361 is a high performance, highly integrated radio
frequency (RF) Agile Transceiverâ„¢ designed for use in 3G and
4G base station applications....
Datasheet
AD9361 on Analog.com
I am experiencing calibration time durations from 10s of milliseconds to seconds. It seems to be due to the PLL lock times. I am running the PLLs at either 960 MHz or 921.6 MHz. Observing the RX PLL lock bit (0x247-bit1) and TX PLL lock bit (0x287-bit1), both stay low after calibration.
How to calibrate with PLLs locking in a few milliseconds?
Are you operating under normal temperatures? Have you tried initializing with the default initialization settings in the driver?
I later learned that the software engineer was using a development board and needed to set his reference_clock_rate = 40 MHz rather than 80 MHz.. Now PLLs behave properly as they did on our target board. Sometimes conditions change and I'm the last to find out! Sorry!