Rx Samples Sync issue after MCS pulse to 4 ICs each with 2 Rx channels

If the DATA_CLK is not synced, then the MCS is not achieved. After the SYNCIN is sent by the FPGA, the DATA_CLK should get synced. Are you giving the same REF_CLK source to all the 4IC's?

Thanks for fast response 

Yes it's same ref clock for all.

How can it be explained that I see that all clock out which are the ~491MHz / 16

Getting synced perfectly? 

Isn't it just a divide by two between our adc (~491MHz)

To the 245 MHz data clock

Is there something else in the path between them?

I give more info

Ref clock from idt clock Gen is

61.38MHz, bbpll makes it x16 around 983Mhz

Adc is 983 /2 =~491MHz

The rx data clock is 245MHz

Ddr 

12 bit I, 12bit Q x 2 Rx Channels

The fpga gets only 3 of the data clocks

Catalina 1, Catalina 2, Catalina 3 are separated

But Catalina 2 and 4 use same mutual data clock due to lake of pins in altera fpga.

2 and 4 always synced and use internal alt lvds pll while the unsynced Catalina 1 and 3 use external pll because they are in different banks. They 1,3 are unsynced with 2,4 and between them selves.

But we currently focus on understanding why while in adc /16

We see a obvious change and sync after mcs, on the data clock 245M we don't see same amount of change neither sync.

We measure with 20gps scope on a resistor at the clock input pin of the fpga, we don't have a dedicated test point for Rx data clock measure on our board.

We deal with this issue very long time, while our other products doing the mcs great, this one with different fpga can't be solved even though we process the same. 

We wait to solve it and to get a big product order but our customer not allow to continue with procurement until we solve the problem.

It's 4 ad9361 on each product,

it would be so much for us if we could get some assistance to solve it or even just indicate what is the reason.

Maybe it's the altera fpga that even not allow us to compile all 4 lvds with int pll and common data clock becusae maybe it's due to the reason that 1,3 are at different blocks.

But to start and telling the customer that the issue is due to the fpga he forced us to use, we firstly need to prove that the 4 ad9361 on our product design has no issue.

That's why I try somehow to understand the relationship between the 491M adc clock path to the 245Mhz data clock. If it's only divide by two so how come we see this strange measure result of adc clock synced and data clock not. 

Can you pls explain what is meant by " Catalina 1 and 3 use external pll "? Can you explain with a block diagram how the sync signal is connected between these unsynced boards?

Refer to the below block diagram for achieving MCS.

Can you share oscilloscope plots of DATA_CLK between two devices vs ADC_CLK between two devices?

Hi please see the attached 2 illustrations

we will provide scope pics soon

General Block Diagram

Inside the FPGA

Hi Adding scope pictures to my above response, 4 last pages of uploaded pdf file

Clock out = ~491MHz /16 (0xB9 at reg 0xA)

the channel numbers correspond to AD9361 (1-4) Numbers on scope

i had issue to upload the picture so i added the pdf.

btw AD9361 2 & 4 are always synced to each other.

1 & 3 sometimes synced to each other and sometimes not, even after MCS.

sometimes very few times we saw they were synced with 2 & 4, but we could find some correlations between our attempts to the results we see.

also changing re 0x06 data clock delay and data delay could not assist us, only sometimes we saw that the frames were synced but not the data

Clock Out before MCS ~ 491MHz/16 (0xB9 at reg 0xA) 

Clock Out After MCS

Data Clock Before MCS ~245/8 Using FPGA Counter till 8

on FPGA PIN

Data Clock After MCS ~245/8 Using FPGA Counter till 8

on FPGA PIN, almost no change, same after several MCS procedure execution

PDF

From the block diagram, looks like there is an extra external PLL that is added to the AD9361 1 and 3. Are you probing the DATA CLK at the output of the external PLL? If yes, then you will not see any sync as these two external PLLL's are not referenced to a common source. Can you probe the data_clk at the output of the AD9361?

Hi,

1. thanks again for your fast responses.

2. we measure the data_clock on the FPGA inputs pins before the ext. for lvds usage pll

see below added updated picture.

3. I would like to add important & new interesting input from today. 

we could achieve for the first time the required sync after MCS but only after dividing the BBPLL freq 

we did it by writing to AD9361 register 0x0A the values such as 0x04 instead of 0x00, i.e. that we reduce the ADC clock rate by factor of 2^4 (2^3 also ok) and only then we achieve sync. its very good step in the debug but we need the product to work at the higher ADC clock rate frequency 

We donot recommend configuring the registers randomly. Use the filter wizard tool to generate a profile with lower sampling rate and hence lower ADC clock rate. Initialize the chip with the same profile and then check for MCS.

https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/filters 

Thanks 

We implemented the change in our init file and then tested it few time and with the low bbpll it synced after mcs.

At our 491MHz it's still not synced.

Of course we will review again with the tool you provided. 

Do you have assumptions about our high rate issue? 

Where is generated the data clock?

Inside the lvds interface based on the adc clock and decimations? 

Are you able to run digital interface tuning successfully at higher rates?

https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/interface_timing_validation