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AD9361 maximum CLK_OUT frequency

Thread Summary

The user wants to use the CLK_OUT pin of the AD9361 to output an 80 MHz clock, but the CMOS mode is limited to 61.44 MHz. The final answer confirms that CLK_OUT cannot exceed 61.44 MHz in CMOS mode. An alternative is to use the REF_CLK input directly, which can be scaled to 80 MHz after a *2 scaling. If CLK_OUT is not used, it can be left floating.
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Category: Datasheet/Specs
Product Number: AD9361

I want to use the CLK_OUT pin of the AD9361 as an input to my FPGA.  I am using an external clock input of 80 MHz, and I would like that 80MHz to come out of the CLK_OUT pin (i.e. set CLKOUT select of Table 9 in UG-671 to 000).  However, in UG-570 that the clock frequency must be less than 61.44MHz.  Does this mean the CLOCK_OUT is clamped to 61.44MHz?  It won't show me a buffered copy of my 80 MHz clock input? 

Thanks,

- Jon

Parents
  • Yes correct, maximum is 61.44Msps.

    You can change the API  adi,clk-output-mode-select  to BUFFERED_XTALN_DCXO in the init parameter structure and then initialize and the CLOCK OUT will give a buffered version of the REF_CLK input.

    You can directly connect the REF_CLK from the external source to the FPGA.

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  • Yes correct, maximum is 61.44Msps.

    You can change the API  adi,clk-output-mode-select  to BUFFERED_XTALN_DCXO in the init parameter structure and then initialize and the CLOCK OUT will give a buffered version of the REF_CLK input.

    You can directly connect the REF_CLK from the external source to the FPGA.

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