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AD9361 maximum CLK_OUT frequency

Category: Datasheet/Specs
Product Number: AD9361

I want to use the CLK_OUT pin of the AD9361 as an input to my FPGA.  I am using an external clock input of 80 MHz, and I would like that 80MHz to come out of the CLK_OUT pin (i.e. set CLKOUT select of Table 9 in UG-671 to 000).  However, in UG-570 that the clock frequency must be less than 61.44MHz.  Does this mean the CLOCK_OUT is clamped to 61.44MHz?  It won't show me a buffered copy of my 80 MHz clock input? 


- Jon