AD9361 maximum CLK_OUT frequency

Yes correct, maximum is 61.44Msps.

You can change the API  adi,clk-output-mode-select  to BUFFERED_XTALN_DCXO in the init parameter structure and then initialize and the CLOCK OUT will give a buffered version of the REF_CLK input.

You can directly connect the REF_CLK from the external source to the FPGA.

I interpret that to mean the CMOS outputs (including the buffer for CLK_OUT) aren't rated/reliable above 61.44 MHz, correct?  I can't imagine there could be a hard lockout that prevented the output from being enabled if the clock is too fast.

I'm not sure that a multi-drop approach for the clock will be feasible in our design.

The maximum DATA_CLK frequency that can be supported in CMOS mode is 61.44Msps.Also, the maximum data rate supported is 61.44Msps. So yes, your interpretation is correct that CLK_OUT cannot be supported for more than 61.44Msps. You can operate the REF_CLK input to 40MHz, then after *2 scaling the actual REF_CLK for the PLL's would be 80MHz.

So if we are not going to use the CLK_OUT pin should we just tie to ground?

CLK_OUT is an output clock pin. You can keep it floating

Thanks!