Problem within the ad9361 IP. TX data out is having weird signed bit issues.

I have custom board for the kria k26c som and the ad9364 chip. I used the fmcomms2 design as a reference for my HDL. I have a petalinux build for it that boots fine and I can transmit data.I can also receive data. I ran a BIST loopback to verify the validity of the data and it seems as if the tx data flips signs every 512 samples for no apparent reason. I transmit a sin wave and I can see this sin wave coming out of the DAC_FIFO in the hdl when i probe it. The data gets messed up somewhere inside the ad9361 IP. I know the problem in on the TX side and not how the data is received because I can use my ad9364-z7020 to transmit data to my custom board and it is received correctly. My ad9364-z7020 design works perfectly fine as I used the provided boot image and put it on my sd card for that board. So essentially I have a working ad9364 based board with the ad9364-z7020 board and a buggy ad9364 in my custom board. The only major difference between the two is the processor. the ad9364-z7020 is on the zynq, my custom board is on the ultrascale +. 

Here are some screenshots showing that the TX side of my custom board is busted.

In this screenshot I am sending one CW TONE at 5mHz, -12DB scale from the DDS on both boards and using the BIST loopback (digital TX -> digital RX) on both boards. The top waveform is ad9364-z7020(zynq), The bottom is my custom board (ultrascale+) the format is such for all other screenshots as well.

This is the same as before except in the time domain. One CW tone.

Sending the same TONE, this is the constellation plot for both. Again ad9364-z7020(zynq) is on the top. 

The next 3 screen shots are my sending a SIN wave via the DAC and looping it back with the BIST digital loopback on both boards. zynq on top and custom on bottom

As you can see the sin wave is going positive and negative for no apparent reason and inverting between positive and negative on my custom board.

Here is a screenshot of me sending the sin wave at -12 db scale, just like with the tone and as you can see it looks a lot better. I think what having the scale at -12db does is get rid of the top bits, not sure about this though, but that is why the TONE looks decent on my custom board because its at -12 db scale.

Now I am going to share some screenshots of my sending data from the ad9364-z7020(zynq) to my custom board to show that the receive is working as intended, and then I will show me sending data from my custom board to the ad9364-z7020 showing that indeed the TX is where the problem is on my custom board.

As you can see the ad9364-z7020(top) is sending a sin wave both to itself via the Digital loopback BIST and to my custom board via a physical connection. You can see that besides some locking and amplitude issues I am receiving a sin wave on my custom board.

Here is me sending from my custom baord (bottom) a sin wave to both itself via the BIST digital loopback and to the ad9364-z7020(top) via a physcial connection. You can see that it shows a similar waveform in both except the receive on the ad9364 is a little noisy because of locking and amplitude and other interference that happens with a physcial connection. This shows that the problem is in the transmit side of my custom board.

Here is a screenshot of the DATA coming out of the DAC fifo going into the AD9361 IP when probed with an ILA in the HDL.

As you can see the output of the DAC fifo is a SIN wave like I expect on my custom board. Further showing that something within the AD9361 IP is wrong.

Looking at the elaborated design for the zynq version of the ad9361 and the ultrascale+ version the only difference I was able to find was this

The ultrascale + uses the OSERDESE3 block while the zynq does not, the zynq uses ODDR1. My hunch is that this is the issue. But im not sure at all.
Another note, TX tuning fails on my custom board if that has anything to do with anything, I skip tx tuning in my device tree for this reason. 
If youd like any more info in order to help me find the issue let me know, this is quite puzzling.