I am building a project around the kria k26c som and the ad9364 chip. I used the fmcomms2 deisgn as a reference. I have the whole build ready and i am using petalinux 2023.1, and the devicetree, meta-adi layers, etc all from 2023.1. Im trying to run a loopback test using the BIST. I am sending a sin wave as data using the DAC in the iio oscilloscope app. When i recapture that Data on the RX side its not a sin wave. it looks like this
The fb_clk p/n pins are inverted physically so I did set register 0x3E to 0x8F. If i dont do that the voltage 1 data is very noisy, idk if it matters as far as the sin wave not being transmitted correctly goes. I did probe the output from the DAC fifo in the HDL and saw a sin wave when I switched the Radix to signed decimal. I have verified that this is a transmit side issue and not a receive side. Since the data coming out of the dac fifo and going into the ad9361 IP is a sin wave im assuming something happens inside the IP causing the data to looks like this. It looks like the 8th bit is signed. As there is a sin wave in there somewhere its just inverted on some bits. I can see this if i set the Scale(DBfs) to -12 for the dac buffer. Upon setting the Scale to -12 DBfs I get the following data being received.
Any ideas on what might be happening? I am bewildered as to why a bit flip/ sign inversion, etc might be happening internally.
