Max freq hop rate using fastlock and SPI (no GPIO)

What is your frequency hoping time requirement? In fast lock mode, the maximum frequency hopping time is 20usec, and this is in pin control mode. 

It's really a question of what's the best we can do.  50us would be great.  The 20us is clearly too optimistic since it does not include the overhead of either loading a new profile or switching it via SPI.  I can (probably) drive the SPI from the FPGA side to remove any OS-related jitter.  

What is the frequency hop step? Is it within 100MHz? If the hop size is more than 100MHz, then you need to run few init cals as well, which will increase the time consumption.

Refer to the below link for timing calculations:

https://ez.analog.com/linux-software-drivers/f/q-a/87914/measuring-the-pll-locking-time/186283?queryID=0a1890a673f51f65d2932a3b9179898a&objectId=798dd265-c356-4d85-b68c-069b21241ff6&eztype=Forum%20Reply 

Thank you for the quick response.  The link is very helpful, and appears to confirm my understanding that a hop will take 16 SPI writes + 20us.  The frequency hop step is > 100 MHz.  Am I correct in assuming that the initial calibration only has to be run once (assuming temperature is stable).

You need to run the below init callibrations if the hop is more than 100MHz, else there will be a degradation in performance:

I am playing with the development board and came across a parameter called 'VCO Cal Count'  If I change it to 0, the PLL calibrates and locks in under 30 us (as measured on a scope).  I am not using the fastlock registers at all.  What am I missing?  Why do I need to bother with fastlock if a regular frequency setting (w/ VCO Cal Count=0) takes about the same amount of time?

VCO Cal Count: These bits set the VCO frequency calibration counter length. 00 = 128, 01 = 256, 10 = 512,11 = 1024.

So, if you are setting the cal count to zero, in that case, the VCO calibrations are done faster and hence the time is decreasing. But in this case, you will be compromising with the accuracy since the cals are run for a shorter time.

In fast lock mode, we are running the VCO cals normally for the set frequencies and storing those values. Later while recalling those frequencies, we are eliminating the VCO cal time by simply recalling those values and not compromising with the accuracy. 

What does "compromising with the accuracy" mean?  If the PLL is locked, it is locked -- i.e. the frequency is correct.  Is the concern that it may not lock?  Or is the phase noise/jitter increased (I don't see why it would).

If the VCO calibration is run for a shorter time, then it may happen that the frequency selection by the VCO is not accurate for over a longer time and also it may impact the phase noise. So, you might have the need to run the VCO cal again after sometime to achieve accuracy.  The speed of the VCO cal, always have an impact on the accuracy.