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Max freq hop rate using fastlock and SPI (no GPIO)

Category: Hardware
Product Number: AD9361

I am working with an AD9361 board (w/ a Xilinx Zynq) that does not provide access to the the fastlock profile selection pins.  This means we can only access the registers via SPI :(.  I need to hop over a wide bandwidth as fast as possible. Has anyone run an experiment that shows the time to 

1. Load a profile from memory over SPI (I have many more than 8 profiles), so after the first 8 are used up, every profile needs to be loaded separately.

   a. The max SPI clock rate is (I think ~50 MHz).   Theoretically loading 16 bytes should only take < 3us.  

2. Send the select profile command over SPI

3. Wait for the PLL to lock.

A ballpark value would be helpful before I go and try it out. Would using the iic interface be appreciably slower than calling the API directly from C++?