AD9361
Recommended for New Designs
The AD9361 is a high performance, highly integrated radio
frequency (RF) Agile Transceiverâ„¢ designed for use in 3G and
4G base station applications....
Datasheet
AD9361 on Analog.com
Please someone guide me on how can I Build HDL in Windows. Actually I am using Vivado on Windows to program my Xilinx Zynq 7000 SoC ZC702 Evaluation Board. So I want to be able to use the AD-FMCOMMS3-EBZ with Xilinx Zynq 7000 ZC702 Evaluation Board on Windows itself. I understand that I need to build HDL for that but to use the 'make' command etc I require would require a Windows Subsystem for Linux (WSL) but when I am trying to use 'make' then it expects the Vivado files to be in Linux format. I don't understand how can I BUILD HDL in Windows. Please Help. Thank you.
I am getting the following errors upon trying to building project ZC702 using make in Cygwin
andrei_g - Moved from Design Support AD9361/AD9363/AD9364 to FPGA Reference Designs. Post date updated from Thursday, February 8, 2024 5:02 AM UTC to Thursday, February 8, 2024 11:19 AM UTC to reflect the move.
andrei_g - Moved from Design Support AD9361/AD9363/AD9364 to FPGA Reference Designs. Post date updated from Thursday, February 8, 2024 11:19 AM UTC to Thursday, February 8, 2024 11:19 AM UTC to reflect the move.
Shivansh - Moved from FPGA Reference Designs to Design Support AD9361/AD9363/AD9364. Post date updated from Thursday, February 8, 2024 5:02 AM UTC to Monday, February 19, 2024 5:42 AM UTC to reflect the move.
Shivansh - Moved from FPGA Reference Designs to Design Support AD9361/AD9363/AD9364. Post date updated from Monday, February 19, 2024 5:42 AM UTC to Monday, February 19, 2024 5:42 AM UTC to reflect the move.
Hi,
All you need is there.
From the second image. "expected 2023.1 got 2023.2" https://github.com/analogdevicesinc/hdl/blob/main/scripts/adi_env.tcl#L18C30-L18C36
Either install 2023.1 or enter export ADI_IGNORE_VERSION_CHECK=1
Andre
Upon running the export ADI_IGNORE_VERSION_CHECK=1 command it does ignore the Vivado version but continuing to Build HDL using 'make' gives following error
ERROR: [Common 17-217] Failed to load feature 'ipservices'.
INFO: [Common 17-206] Exiting Vivado at Thu Feb 8 07:49:53 2024...
Hi Shivansh ,
Did you check out our build guide? https://analogdevicesinc.github.io/hdl/user_guide/build_hdl.html
While being in the hdl/projects/fmcomms2/zc702 folder, could you please run make clean-all and then run make again?
It shouldn't happen again, but let me know how it goes.
Best regards,
Iulia
Please also check out this answer from another user who experienced this error previously: RE: ADALM PLUTO SDR Custom VHDL
Hello,
Now that I have built HDL for my FMCOMMS3-EBZ and Zynq 7000 SoC ZC702. What do I do next can someone please guide to how to use Vivado and get some RF Signal output from the system. Please keep in my mind that I am using Windows. I just want to understand on how to get started here. And Thank you iulia and andrei_g for your inputs, they have been extremely helpful.
Hi Shivansh ,
Unfortunately, we cannot help you with Vivado since this is not our tool. For this, you would have to go through their user guides or tutorials. They have many on this topic.
Best regards,
Iulia
Regarding RF signals see the common user guide https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz.
For Vivado, as Iulia noted you have to go through AMD(Xilinx) documentation/tutorials.
Andrei