AD9361 External Reference Issue

Hello,

I describe our settings : A signal generator delivering the REF_CLK is connected to both the FMCOMMS3 board and one channel of a scope. Another channel of the scope is connected to the DATA_CLK signal. The scope is in the trigger mode on the REF_CLK signal. The REF_CLK frequency is either 40 MHz or 62.5 MHz (the clock- frequency parameter is modified as required for each case in the device tree).The DATA_CLK frequency stays at 12 MHz as define in the clock path. The chip is initialized in each case and we look at both channels on the scope. What we see is that for a 40 MHz REF_CLK, the two traces are stable on the scope. For 62.5 MHz, the REF_CLK displayed on the scope is stable because this is the trigger signal, and the 12 MHz DATA_CLK signal is sliding in time.
We are not trying to measure a delay between the two traces but just want to see if they are synchronous, which is not the case for REF_CLK = 62.5 MHz.

You indicates that REF_CLK and DATA_CLK must be integer multiple for a good measurement but it is never true in our two cases.

The ratios are 40/12 = 3.33 or 62.5/12 = 5.21. For the first ratio the two traces are stable on the scope but not for the second as if the BBPLL chain that deliver the DATA_CLK was not locked. We expect to see two stable traces for both measurement. Do you agree with that ?

I try to send you a small vids of what we see as soon as possible.

Best Regards

Instead of vids, I send you two screen plot of the scope.
On the first image you can see on the upper trace the 48 MHz DATA_CLK signal (4 x RSAMPL in 2R/2T LVDS Mode) which is the trigger signal and on the lower trace, a 80 MHz REF_CLK. As you can see in this case, the traces are synchronous.
On second image, we use a 62.5 MHz REF_CLK. In this case, the lower trace (REF_CLK) is impossible to be clearly displayed because it is asynchronous with DATA_CLK.
Normally we should see the same kind of trace than the first plot for REF_CLK with just less period.
This is why we conclued that for a 62.5 MHz REF_CLK, there is a problem of locking in the BBPLL path.
Do you confirm on your side ?

We tested the same on our eval board and was able to see the same behavior. The DATA_CLK is sweeping in time with respect to the REF_CLK signal, when they are not integer multiples of each other.

We have not seen customers facing any issue because of non integer multiples as the PLL's are fractional PLL's. Are you facing any issues with data demodulation when they are not integer multiples?

No, we do not have problem in a single channel configuration. Recently we have been able to do some measurments on our own board equiped with 2 x AD 9361 drived by the same REF_CLK. We do not see any asynchronism between the two DATA_CLK signals ! 

It seems we were misled by the measurement method on the FMCOMMS3 board.

At any rate, thanks for your support ! 

Ran_63 said:

We do not see any asynchronism between the two DATA_CLK signals ! 

Yes, DATA_CLK 's between multiple boards will be synced w.r.t each other after the SYNC signal turns high because of the baseband multichip sync feature.