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AD9361 External Reference Issue

Category: Hardware

We are using the FMCOMMS3 board with an external reference frequency of 62.5 MHz. All the modifications on the hardware and the device tree have been done as required.
At power up the path clock frequencies is as follow :
BBPLL 768 MHz, ADC 48 MHz, R2CLK 24 MHz, R1CLK 12 MHz, CLKRF 12 MHz, RSAMPL 12 MHz.
When we display the external reference and the DATA_CLK signals on a scope we observe that the two signals are not synchronous. One is shifting in time regarding the other. The register of the BBPLL indicates that the PLL is locked.
May we have some support to understand where the problem come from ?
Thanks a lot for replie !