・We are setting Fast AGC mode.
・We are sending signals from FPGA to RFIC and instructing to set EN_AGC to High once the reception is completed.
・When EN_AGC is set to High, does the AGC gain reach its maximum level?
・If not, which settings should be adjusted to achieve the maximum gain?
// Setting value
Ex) Register Address: value
0x0FA: E5
0x0FB: 48
0x111: 2B