Post Go back to editing

AD9361: AGC reset operation

Category: Hardware
Product Number: AD9361

We are setting Fast AGC mode.

・We are sending signals from FPGA to RFIC and instructing to set EN_AGC to High once the reception is completed. 

・When EN_AGC is set to High, does the AGC gain reach its maximum level?

・If not, which settings should be adjusted to achieve the maximum gain?

 

// Setting value

Ex) Register Address: value

0x0FA: E5

0x0FB: 48

0x111: 2B

  • You can set the below registers, if you want to set the gain to maximum when EN_AGC is pulled high

  • Thank you for your response to my previous inquiry. I have a few more questions that I would like to ask.

    Firstly, I would like to know where I can find more information about OptimizeGain. I am interested in learning more about it, so any specific resources or references you can provide would be greatly appreciated.

    Secondly, I would like to understand the transition state when EN_AGC becomes high and gain reaches its maximum in Figure 25. Could you please provide details on which state it transitions to in this scenario?

    Lastly, I am curious about the difference between EnergyLost and another variable. I would like to know what sets them apart from each other.

    Thank you in advance for your assistance. I look forward to your prompt response.

  • Firstly, I would like to know where I can find more information about OptimizeGain. I am interested in learning more about it, so any specific resources or references you can provide would be greatly appreciated.

    Optimize gain sets or locks the gain index after unlocking to the gain of the last burst of the signal. Refer below table from UG for more details:

    Secondly, I would like to understand the transition state when EN_AGC becomes high and gain reaches its maximum in Figure 25. Could you please provide details on which state it transitions to in this scenario?

    When EN_AGC is pulled high, the gain unlocks and the AGC algorithm will restart, but in this case, the gain will be set to optimize gain(or max gain or set gain, depending on the settings) in state 5 of fast AGC.

    Lastly, I am curious about the difference between EnergyLost and another variable. I would like to know what sets them apart from each other.

    Energy lost condition occurs when there is a huge decrease in signal amplitude.

    Refer to "Fast Attack AGC Mode" section in UG for more details

  • I am very grateful for your response to my question.

    Although I have made the settings according to the response to my question, there is a malfunction.
    Specifically, the signal is coming from the FPGA to EN_AGC, but the gain is not reaching its maximum level.
    Are there any possible causes that you can think of?

  • Sorry for the delay in response. 

    Are you still facing the issue?

    If yes, when the EN_AGC is pulled  high, is the AGC unlocking and are you monitoring the AGC state to which it is going to and also the signal at the output? Can you share with us a signal capture in time domain, where the AGC is unlocking in response to EN_AGC and then settling down? How are you ensuring that the gain is not reaching maximum levels after unlocking?'

  • I apologize for keeping you waiting for so long.
    I are sorry, but we cannot provide content such as screenshots.
    After thinking about this issue a lot, I realized that the API control "fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en" seems to solve the problem.

    So, there is something new that I would like to confirm:
    What is the meaning of "fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en"?
    And which value, 0 or 1, should be used to unlock the gain when energy is lost?


  • What is the meaning of "fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en"?
    And which value, 0 or 1, should be used to unlock the gain when energy is lost?

    A value of 1 would be used to restart the FAST AGC algorithm when the signal power is so low that it exceeds the energy lost threshold.

  • Thank you for replying my question. I understand the meaning of  "fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en".

    I would like to set a register value so that the operation is forced when EN_AGC goes High,

    regardless of whether the IC experiences energy loss or not.

    How should I set it up?

  • You can use the EN_AGC pin , connect it to the BBP and pull that pin to high, if you want to unlock the AGC irrespective of input signal conditions.

    From UG:

    However, in some situations, it may be advantageous for the BBP to initiate an unlock condition. If the BBP pulls the EN_AGC pin high, the gain will unlock and the AGC algorithm will restart. The BBP cannot force the gain to lock at a certain time but it can control when the gain unlocks. Table 25 shows how to use this feature.

  • I understand that BBP stands for BaseBand Prosessor, which is an external input (FPGA as an example).
    So my question is, which one means "EN_AGC Pin Is Used" in Table.26?
    ・EN_AGC is connected as wiring. (Even if there is no signal input, it will be Yes)
    ・It becomes "Yes" when a signal is input to EN_AGC?

    Furthermore, does this specification give priority to EN_AGC or EnergyLost for AGC reset operations?