In a frequency sweep application with steps of 40MHz (for example). It seems the PLL should (more) quickly settle if the previous frequency was close to the new frequency (40MHz away) so I don't always need the full setting time. Am I missing something here? Over the course of my sweep change the divider will change so I expect thecorresponding large PLL frequency transition would need the maximum settling time. I am trying to sweep as quickly as possible. I am also considering setting aside several fastlock entries for the several divider change locations so I can quickly set these special frequencies to save SPI time.