Regarding the multiple AD9361 reference clock input using 1:8 clock divider

Yes above method is recommended and ADCLK846 is the part used in the FMCOMMS5 board, you can refer to the AD-FMCOMMS5 schematic.

https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms5-ebz.html

Please ensure to meet the input clock requirements for the AD9361.

Hello, 

Thank you for the quick response.

Hi, 

I have gone through the ADCLK846. My actual requirement is to provide 10 MHz external clock to the ADCLK846 and generate 8 single ended CMOS outputs having 1.3 VP-P output and have output SMA connectors. further the ADCLK846 outputs needs to be provided through external RF cables to all AD9361. 

In order to interface ADCLK846 outputs to AD9361 through SMA connectors and cables, we need to take 50 ohm impedance, right? or what extra care needs to be taken care to have the highest isolation between each outputs?

ADCLK846 output is CMOS/:LVDS and not 50 ohms, please refer to the datasheet for the termination and use as needed., also it is recommended to keep the clock and transceiver on the same board.

A 10 MHz external reference clock for AD9361 is not recommended and always better to use above 20 MHz.

Hello

Thank you for the quick response.

As there will be an individual 8 custom boards having AD9361+FPGA . each individual board is having 1 external clock input provision. so that's why I am planning to use external clock distribution system that can provide 10 clocks to each individual boards. Is there any suitable solution on how to provide external clocks to individual boards through clock distribution system. 

And if 10 MHz is not recommended , then I think I need to use multiplier to convert it to higher frequency as my external input will be 10 MHz only. 

Awaited your response.

Hello

Thank you for the quick response.

As there will be an individual 8 custom boards having AD9361+FPGA . each individual board is having 1 external clock input provision. so that's why I am planning to use external clock distribution system that can provide 10 clocks to each individual boards. Is there any suitable solution on how to provide external clocks to individual boards through clock distribution system. 

And if 10 MHz is not recommended , then I think I need to use multiplier to convert it to higher frequency as my external input will be 10 MHz only. 

Awaited your response.

Hi Maitry,

You could use the FPGA's PLL to make higher clock frequency for the ADC from the 10MHz reference clock. If lucky, the PLL will reduce jitter too, and it is easier to interface the ADC to FPGA, when the clock is provided by the FPGA.

It is fine to use SMA+coaxial for the LVCMOS clock. At 10MHz you do not need to worry about matching to 50 ohms (if the clock has fast edges that seem to ring, you can use 50 ohm matching for harmonics, i.e. a small cap + 50ohm resistor in series shunting the receiver end).

Cheers, heke

Hi Heke,

Thank you for your response. 

so, if I want to use ADCLK854 clock divider as an external pcb and try to provide 10 MHz clock to each AD9361. then would it be proven to have proper performance with 10 MHz or else should I go for at least for 20 MHz clock?

Awaited your response.

Hi Heke,

Thank you for your response. 

so, if I want to use ADCLK854 clock divider as an external pcb and try to provide 10 MHz clock to each AD9361. then would it be proven to have proper performance with 10 MHz or else should I go for at least for 20 MHz clock?

Awaited your response.

Hi Maitry,

According to the specification, 10MHz reference clock is fine. As the chip seems to have own fractional-N PLLs, the clock jitter is more important parameter than the frequency.

Cheers,

heke