Category: Hardware
Product Number: z77035 , AD9361 ,adrv9361-z7035
Software Version: vivado 2019.1 , HDL_2019_r2
Dear All,
I have designed a system based upon HDL_2019_r2 reference design and ADRV9361_z7035 board. My logic include to search peak in particular bandwidth but I am facing issue with Tx LO leakage. TX LO inject leakage in Rx path which create false positive for peak search algorithm .so it is possible to suppress Tx LO as much as possible ? My application required RX and TX LO need to be closed as much as possible . I am also power downing TX LO via script when the system in scanning mode . is there better way to deal with TX LO leakage ?