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# Phase ambiguity caused by VCO divider

Category: Datasheet/Specs

Hello,

in this link, the user mentioned a webinar that explains phase ambiguity as "Sync pulse does not synchronize the divide by 2 array (pictured below), meaning each division can occur on either the rising or falling edge of the clock. This introduces a phase ambiguity dependent on the division ratio. Divide by 2, can only have a phase ambiguity of 0 or 180"

as far as i know, 180-degree phase difference means that signals are inverted versions of each other. in divide by 2 case, division may occur in posedge or nedegde and this causes 90-degree difference. so, should it be 90 or 0? or am i missing something?

cheers,

dea

• During divide by 2 operation, the division can start either the first way or the second way w.r.t the actual Reference clock. So,it is said that there can be a phase ambiguity of either 0 degree or 180 degree.

• thanks for the explanation.

i have one more question regarding how this difference affects received signal amplitude.

in https://wiki.analog.com/university/tools/pluto/users/non_quad, it is written that "Here the amplitude difference between I & Q is random based on the random difference between the phase of the Rx and Tx PLL. This is indeed completely random and will change any time either PLL settings are touched. Moving one LO to a different setting, and back again, will change this phase offset (which manifest itself as a magnitude difference between I and Q)."

moreover, in https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/math, output of complex modulation is given as . my question is K parameter is affected by phase difference so it causes an amplitude difference in the received signal?

regards,

dea

• my question is K parameter is affected by phase difference so it causes an amplitude difference in the received signal?

Yes understanding is correct