Category: Datasheet/Specs
Hello,
RE: Phase Difference in AD9361 Multichip Synchronization
in this link, the user mentioned a webinar that explains phase ambiguity as "Sync pulse does not synchronize the divide by 2 array (pictured below), meaning each division can occur on either the rising or falling edge of the clock. This introduces a phase ambiguity dependent on the division ratio. Divide by 2, can only have a phase ambiguity of 0 or 180"
as far as i know, 180-degree phase difference means that signals are inverted versions of each other. in divide by 2 case, division may occur in posedge or nedegde and this causes 90-degree difference. so, should it be 90 or 0? or am i missing something?
cheers,
dea
. my question is K parameter is affected by phase difference so it causes an amplitude difference in the received signal?