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Phase ambiguity caused by VCO divider

Category: Datasheet/Specs


 RE: Phase Difference in AD9361 Multichip Synchronization 

in this link, the user mentioned a webinar that explains phase ambiguity as "Sync pulse does not synchronize the divide by 2 array (pictured below), meaning each division can occur on either the rising or falling edge of the clock. This introduces a phase ambiguity dependent on the division ratio. Divide by 2, can only have a phase ambiguity of 0 or 180"

as far as i know, 180-degree phase difference means that signals are inverted versions of each other. in divide by 2 case, division may occur in posedge or nedegde and this causes 90-degree difference. so, should it be 90 or 0? or am i missing something?