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AD9361 Recommended for New Designs
The AD9361 is a high performance, highly integrated radio frequency (RF) Agile Transceiverâ„¢ designed for use in 3G and 4G base station applications....
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AD9361 IQ swap setting

gang68 on Jul 23, 2021

Hi，

just double confirm：

for AD9361 SPI register 0x010, set bit 6(&7) = 0 means swap IQ, right？

so if I don't want to swap IQ, I should set bit 6(&7) = 1, right? thank you!

asking this quesiton, because when I set 0x010 = C8, I found the IQ is swapping, anyone met similar situation? thanks!

B.R.

Gordon

srimoyi

on Jul 29, 2021 10:52 AM
0
Are you using BIST to send tone? Disable BIST and send tone from FPGA and see whether you are still seeing the swap with bit 6 and 7 set to 1?

https://ez.analog.com/wide-band-rf-transceivers/design-support/f/q-a/106940/ad9361-i-q-data-swap/317524#317524
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gang68 on Aug 2, 2021 2:47 AM in reply to srimoyi
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thanks, Srimoyi!

1. We don't use BIST;

2. We use normal application - FPGA send tone to 9361;

for this use, and from the link you provided, set bit 6&7 =1 by default, that means I Q swap, right? can you confirm? thanks!

B.R.

Gordon
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srimoyi

on Aug 8, 2021 12:25 PM in reply to gang68
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For normal application, setting Bit 6 and 7 to default 1, means that there is no IQ swap.

For BIST, setting Bit 6 and 7 to 1, means that there will be an IQ swap.

Make sure that you have no inversion in your data port connection, if you are using custom board.
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gang68 on Aug 9, 2021 8:57 PM in reply to srimoyi
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thank you very much, Srimoyi!

I will double check with eval board.
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AD9361 IQ swap setting

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