I have posted my original query in another forum by mistake.
https://ez.analog.com/partnerzone/f/q-a/542437/ad9364-cmos-line-length-matching-requirement
It is understood that the data lines need to have approx same length to avoid signal skew issues and the total capacitive load of these signal paths to be less than 3PF at max sampling rate.
In the ADALM pluto,all the CMOS data lines are having a length of approx 23mm.My drought is why the length of the Rx DataClock & Frame signals have a trace length of approx twice as that of the data lines and Tx (fb) clock and frame signals having a length approx same as those of data lines in ADALM pluto design.
Is it becaz of routing constraint or it was done intentionally?
