Hi everyone,
This is my first post. I am very new to RF field. Sorry for some easy concepts.
Before posting this question I searched a lot but couldn't find a solution to my problem so if there are similar posts please accept my apologies.
I have started working with a setup consisting of Xilinx Zc0702 Zynq board connected to FMCOMMS5 RF board. I also have an external signal generator. I'm using Vivado 2018.3 version.
I created the base hdl project of fmcomms5/zc702 and also application project and it seems working. I get help dialog from serial connected to zynq and can get and set
values using defined commands. I can also see the exact values from sine lut defined in the dac_core.c by addding appropriate ila debug cores and opening #define DAC_DMA_EXAMPLE.
When I connect the ila to adc outputs of both ad9361 IP cores I see a constant sine wave from all channels. When I change rx_lo_freq and tx_samp_freq using terminal there is some change
with those waveforms. Where does exactly that data come from?
When I connect the signal generator to one of fmcomms5 's rx input connector and change the freq and and amplitude of the input signal there is no change in any of those waveforms.
How can I capture the signal generator's output correctly? Any help will be appreciated. Thanks in advance . . .
uguden
