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AD9363 Recommended for New Designs
The AD9363 is a high performance, highly integrated RF agile transceiver designed for use in 3G and 4G femtocell applications. Its programmability and...
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AD9363 on Analog.com

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No data clock in CMOS mode

s.kannan

on Feb 28, 2020

We are using AD9363 in our project with the CMOS data interface between AD9363 and FPGA.

There is no data clock output from AD9363 when CMOS mode(disable the LVDS mode) is enabled, but the BIST tones are working fine.

When we enabled LVDS mode in the AD9363 configuration, we are getting the data clock from AD9363. Can anyone help us in identifying the issue?

0 srimoyi

on Mar 2, 2020 2:42 AM
Are the RX and TX paths working good in CMOS mode(check by sending a tone into TX or RX input)?Hope you are grounding FB_CLK_N pin as per recommendations in datasheet.
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0 s.kannan
on Mar 3, 2020 12:30 AM in reply to srimoyi
FB_CLK_N pin is grounded as recommended. We couldn't send any tone at Tx as the FPGA isn't getting any data clock from AD9363 for it to send the FB_CLK. Is there any other parameter that needs to be tuned?
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0 srimoyi

on Mar 3, 2020 12:50 AM in reply to s.kannan
Hope you are aware of the lower driving strength of CMOS mode and that it cannot be routed to long distances. Refer to the below link:

https://ez.analog.com/wide-band-rf-transceivers/design-support/w/documents/10066/ad936x-digital-interface-capacitive-load-drive-in-cmos-mode

Hope you are setting the 0x12 register to 0x04 to enable CMOS mode.
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No data clock in CMOS mode