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Tx Monitor I/Q output

Hello,

I want to use the AD9364 in TDD Tx, activating the Tx Monitor path, and getting the resulting I/Q data on parallel port:

For that purpose I have configured the parallel port in  CMOS-DDR-FullDuplex-Full Port : register@0x012 = 0x02

=> so on P1: I sent the Tx data to AD9364 with I/Q muxed => OK

=> and on P0: I should see the Rx data from AD9364 with I/Q muxed 

My config:

when in TDD, I activate the Tx Monitoring path using  ad9361_set_rx_rf_port_input with RFport=9 (TX_MON1 selected) and I have activated the Enable Rx Data Port bit (D7 of register@0x014)

=> I was expected to see some Rx I/Q data on P0 coming from the Tx Monitoring path but the port seems in High Z, no Rx Frame signal, no data toggling => KO

(please note that this is OK when the AD9364 is set in FDD, I receive the data correctly) 

I did a check on various registers but did not see any issue, here are the values: 

register[0x1]=0x0 

register[0x12]=0x2  //CMOS-DDR-FullDuplex-Full Port

register[0x13]=0x0 // TDD mode

register[0x14]=0xA9  //Enable Rx Data Port

register[0x57]=0x38 // Tx Monitor Power Down = 0

register[0x6E]=0x29 // Tx Mon enable

Questions:

- why I can not see the I/Q data coming from the Tx Monitor path? 

- is there a mistake in the parallel port config for such feature?

- is there other registers to be checked to confirm the correct settings?

- also I'm not confident into the Tx RSSI value reported so wondering if the Tx Monitoring path is really activated....

thanks in advance for your help,

Mikael

Parents
  • TPM Test mode. (I,Q data out using TPM port)

    If the application is TDD, it is not possible to output TPM IQ data on the RX data port as the TDD state machine is overriding the 0x14[D7] bit and is not enabling the Rx port for data transmission. But this is possible in FDD mode, where both the data paths are enabled. Steps for doing this are:

    • Register 0x001[D6:D5] – set the Bits high.
    • Register 0x014 Bit D7 (Enable Rx Data Port) - needs to be set high.
    • Register 0x06E Bits D7 and D5 (TPM Enable) - needs to be set high.
    • Register 0x057 Bits D2 and D3  ( Analog Power Down Override) – needs to be cleared

    TPM(TX RSSI) is possible in TDD and FDD mode, for TDD mode is as explained in UG but for FDD mode set Register 0x001[D6:D5] – set the Bits high

    Please refer below,

    https://ez.analog.com/wide-band-rf-transceivers/design-support/w/documents/10058/transmit-power-monitor-tpm-ad936x

Reply
  • TPM Test mode. (I,Q data out using TPM port)

    If the application is TDD, it is not possible to output TPM IQ data on the RX data port as the TDD state machine is overriding the 0x14[D7] bit and is not enabling the Rx port for data transmission. But this is possible in FDD mode, where both the data paths are enabled. Steps for doing this are:

    • Register 0x001[D6:D5] – set the Bits high.
    • Register 0x014 Bit D7 (Enable Rx Data Port) - needs to be set high.
    • Register 0x06E Bits D7 and D5 (TPM Enable) - needs to be set high.
    • Register 0x057 Bits D2 and D3  ( Analog Power Down Override) – needs to be cleared

    TPM(TX RSSI) is possible in TDD and FDD mode, for TDD mode is as explained in UG but for FDD mode set Register 0x001[D6:D5] – set the Bits high

    Please refer below,

    https://ez.analog.com/wide-band-rf-transceivers/design-support/w/documents/10058/transmit-power-monitor-tpm-ad936x

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