AD9361 I/Q data swap

Yes there is an internal swap in the case of BIST that causes this issue.

You can clear the bit 6(PP RX SWAP IQ) of 0x10 to eliminate this swapping issue in BIST mode.

Hello,
do I understand that right that by clearing bit 6(PP RX SWAP IQ) I just disable the swap which is set by default? I have proven that by observing LVDS signal and now it matches - Figure 79 from UG-570 with the BIST settings. 
However real  RF test  (bit6 still clear) with CWlo+10 kHz positive offset provides negative 10kHz offset in baseband signal (spectral inversion).

Can you confirm that mentioned swap is related only to BIST and not to the RF signal processing?

Which configuration (BIST or RF signal processing) and 0x010 register settings the "Figure 79. Receive Data Path, LVDS" is valid for?

Can you confirm that mentioned swap is related only to BIST and not to the RF signal processing? Yes, clearing bit D6 only needs to be done in case of BIST.

Do I understand that right that by clearing bit 6(PP RX SWAP IQ) I just disable the swap which is set by default? Yes, correct. The default setting of swap is required for proper reception of the I and Q data in case of real RF testing. Disabling of the swap is required for testing with BIST. Figure 79 is valid in both cases(BIST case- disable the bit real RF testing case-enable the bit )