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Adding my own DPD module to FMCOMMS2 HDL

I have built the FMCOMMS2 HDL code and I have a few questions.

1) Where is the best place to get information on what the AD IP modules do and their interface (read the code maybe?)
2) What AD937x  interface  mode is being used to talk to the IP (FDM dual port?).
3) Where would be the best place to get access to the TX and RX stream in a deterministic way?

Bit of background. I am trying to add a simple Transmitter Digital Pre-distortion module to the AD HDL code.
To do that I need access to the TX samples and RX (tx monitor) samples, the TX and RX samples need to
maintain alignment so I can distort the TX samples and then update the LUT from the RX (monitored) samples.
I am currently thinking of intercepting the samples between the de-multiplex block and the FIFO block.

Unfortunately because I need to do the correction on oversampled data I won't be able to use some of the features
on the transceiver chip. I am using a Zedboard and an FMCOMMS4 board but I won't need symbol rates above 4 MS/s.

The transmitted waveform is DVB-S2 which is a single carrier QPSK - 32APSK waveform.

Yes I know AD do a transceiver with integrated DPD but that is a bit expensive for this application which is to provide a
high power DVB-S2 signal into the Es'hail 2 Geostationary satellite Amateur Radio Wideband transponder uplink on 2.405 GHz.

- Charles



Corrected interface mode to Full Duplex Mode (FDM)
[edited by: g4guo at 11:23 AM (GMT 0) on 30 Dec 2018]

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  • That is most helpful thanks. I now have another question this is to do with the synthesisers on the AD9364.


    Obviously for DPD the monitor receiver ideally should use the same synthesiser as the transmit channel.
    However on the AD9364 while sharing the same reference oscillator the TX and RX synthesisers are separate.

    If programmed identically will there be a phase jitter between the TX and RX channel ?

    If there is a constant phase offset I can compensate for that but if it is pseudo random then I am probably wasting
    my time. I have spoken to a colleague of mine that thinks that as the synthesisers are fractional-N there maybe an issue.

    - Charles

  • AD9361 does not include internal RF synchronization internally and needs a little help.

    There are two methods to solve this issue:

    1. measure the phase difference in the internal LOs, and correct in the FPGA

    https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms5-ebz/multi-chip-sync

    https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/iq_rotation

           2. use an external LO signal.

    You can use same  ext_lo source for both Tx and Rx of AD9364. Then you have to take care of constant phase offset of 180 degree from internal LO divider during power on/off or reset.

  • Thanks, having read the first link it seems that once configured and SYNC_IN performed all the PLL counters etc are aligned and the phase should remain constant.

  • #1 may not be still good for DPD. 

    You need to have same LO for both Tx and feedback and external LO is a better option. Again this depends on DPD algorithm and accuracy/correction targeted. 

  • Yes I was coming to that conclusion. I have an FMCOMMS4 board and I notice that the RX and TX LO inputs are brought out to TPs so that is probably a better idea as I only need it to operate at 2.4 GHz. I also now think that the SYNC_IN is for synchronising multiple devices and that a single device RX and TX chain are locked together already (if the block diagram is right). The SYNC_IN on the FMCOMMS4 board is terminated in a 10K resistor so I would have to modify the board to gain access to that.

  • Just wanted to add that you can use the TXMonitor inputs. In this mode, the part feeds the TX LO into the RX path. You lose the LNA but you don't really need that for DPD.

    To do the necessary time alignment you likely have to use a farrow filter to give fractional sample offset estimation. This is pretty common for DPD.

    -Travis

  • Travis, I have just looked at the AD9361 block diagram and that looks like the proper way to do it as you say I have plenty of signal available. The next challenge is to figure out whether it can be done using iio or whether I will have to modify registers directly. The FMCOMMS4 board brings out TX mon to a not fitted SMA.

    I am planning to do the filter update calculations on the ARM cores in non real time with the PS running a tight loop requesting a new block of TX / MON samples when it can.

    - Charles

  • I am back working on this again. I believe to use the TX_MON input I need to select TDMA mode rather than FDMA mode but I can't see how to do that using libiio

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