AD9364
Recommended for New Designs
The AD9364 is a 1 x 1 channel high performance, highly integrated RF Agile Transceiver™. Its programmability and wideband capability make it ideal for...
Datasheet
AD9364 on Analog.com
I am trying to assess the PlutoSDR (AD9363/AD9364) TX phase noise as a function of external reference clock frequency.
My problem is that I get varying results from one measurement to another, with two phase noise conditions shown in the attached chart
My initial thought was that I was obviously doing something wrong with the measurement, so I reproduced the measurement with a Rohde & Schwarz FSWP phase noise analyzer and an Agilent E5052B and both instruments exhibit the same behavior: most of the time I get the while noise around -80 dBc/Hz, and sometimes the phase noise drops to -110 to -120 dBc/Hz, as seen on the figure above. The reference clock is generated by a Rohde & Schwarz SMC100A (shown as orange baseline curve) with an output power of +6dBm (1.3Vpp as required by the external ref clock), here tuned to 10 MHz. In all cases my output frequency is 100 MHz (I tried outputting 113 MHz in case the 10th harmonic of the reference clock was mixing with the PlutoSDR output, but that did not change anything).
My problem is that I am trying to understand the impact of the LO frequency on the output phase noise, and these inconsistent results make the conclusion hard to reach. Indeed the PlutoSDR is using a 40 MHz Rakon TCXO as a reference clock, and 40 MHz does seem to provide the best solution, but I'd like to quantify the impact of LO frequency and ideally understand why 40 MHz is the best solution (since most reference clocks are 10 MHz, that means introducing some shaping circuit between the reference oscillator and the AD9364 intput). Some preliminary results are shown below, but I am not sure these results are correct due to the lack of reproducibility stated above.
In this measurement, the reference is generated by a R&S SMA (rather than the more noisy SMC used in the previous experiment).
In my setup a continuous stream of constant-valued I/Q coefficients are sent by GNU Radio to the PlutoSDR at a rate of 875 kS/s. Can the lack of reproducibility be due to some dropped I/Q data when the computer is randomly busy (e.g. networking -- although i have been careful not to use the computer running GNU Radio during the measurements) ? I cannot understand in such a case why only two possible spectra are shown (-80 or -110 dBc/Hz white noise), nor why longer correlations would not end up reaching the same level.
Any comment on the accuracy of these charts would be most welcome. Thank you.
After quite some struggle, I finally achieved some reasonable (I believe) and consistent measurements. The short lesson: don't use a damaged chip for phase noise measurements :)
I believe that early in this phase noise characterization endeavor, I fed the AD9363 of one of my PlutoSDR with a +18 dBm (5 Vpp) reference clock. Reading the datasheet prior to connecting the signal might have been a good idea, but why bother ... I probably fried some of the clocking circuitry. I would be very curious in knowing what part of the silicon was damaged and how it affected the phase noise behavior, but that is well beyond my expertise (it does put in perspective though the basic assumption that digital electronics is unconditionally stable over time, unlike analog components, although it could be argued that the clocking circuitry is analog and not digital).
Following more and more inconsistent measurements, I decided to sacrifice another brand new Pluto for these measurements, and now I have a set of nicely reproducible and consistent measurements as shown below.
1/ 100 MHz output phase noise as a function of input frequency (all generated by a Rohde & Schwarz SMA100A referenced to a hydrogen maser for "long term" stability unless noted otherwise in the legend -- OCXO is a HP10811 OCXO and Rakon TCXO is your original oscillator).
now I understand why the 40 MHz Rakon oscillator was selected (lowering the input clock frequency increases phase noise) and this chart exhibits the long term drift of the TCXO with respect to the maser reference (below 100 Hz). I also tested an HP OCXO scavenged from an old frequency counter which gives consistent far-from-carrier stability measurements with the R&S SMA but improved long term stability wrt to the Rakon TCXO. I should probably have multiplied by 4 the OCXO prior to feeding the Pluto for optimal performance.
For fun I tested the dependence of output phase noise with input oscillator power (ie increased clock jitter with lower power): again consistent results:
and finally I compared various frontends to assess the performance of ADI's solution and its implementation on various boards:
so the B210 and the Pluto behave pretty much the same, drifting on the long term but nice stability on the short term (wrt to Lime), and the 10 MHz OCXO compensating for the long term drift but degrading the short term stability.
I'd really be curious in understanding how the initial chip was damaged by the excessive input power and why the resulting behavior seems to enhance the phase noise dependence on input clock frequency.
Thanks for the amazing development platform (Pluto), JM
After quite some struggle, I finally achieved some reasonable (I believe) and consistent measurements. The short lesson: don't use a damaged chip for phase noise measurements :)
I believe that early in this phase noise characterization endeavor, I fed the AD9363 of one of my PlutoSDR with a +18 dBm (5 Vpp) reference clock. Reading the datasheet prior to connecting the signal might have been a good idea, but why bother ... I probably fried some of the clocking circuitry. I would be very curious in knowing what part of the silicon was damaged and how it affected the phase noise behavior, but that is well beyond my expertise (it does put in perspective though the basic assumption that digital electronics is unconditionally stable over time, unlike analog components, although it could be argued that the clocking circuitry is analog and not digital).
Following more and more inconsistent measurements, I decided to sacrifice another brand new Pluto for these measurements, and now I have a set of nicely reproducible and consistent measurements as shown below.
1/ 100 MHz output phase noise as a function of input frequency (all generated by a Rohde & Schwarz SMA100A referenced to a hydrogen maser for "long term" stability unless noted otherwise in the legend -- OCXO is a HP10811 OCXO and Rakon TCXO is your original oscillator).
now I understand why the 40 MHz Rakon oscillator was selected (lowering the input clock frequency increases phase noise) and this chart exhibits the long term drift of the TCXO with respect to the maser reference (below 100 Hz). I also tested an HP OCXO scavenged from an old frequency counter which gives consistent far-from-carrier stability measurements with the R&S SMA but improved long term stability wrt to the Rakon TCXO. I should probably have multiplied by 4 the OCXO prior to feeding the Pluto for optimal performance.
For fun I tested the dependence of output phase noise with input oscillator power (ie increased clock jitter with lower power): again consistent results:
and finally I compared various frontends to assess the performance of ADI's solution and its implementation on various boards:
so the B210 and the Pluto behave pretty much the same, drifting on the long term but nice stability on the short term (wrt to Lime), and the 10 MHz OCXO compensating for the long term drift but degrading the short term stability.
I'd really be curious in understanding how the initial chip was damaged by the excessive input power and why the resulting behavior seems to enhance the phase noise dependence on input clock frequency.
Thanks for the amazing development platform (Pluto), JM
