Q&A

by Vipin
Design Support AD9361/AD9363/AD9364

Latest 5 hours ago by Vipin
119 2 0
Answered
AD9361 BBPLL Calibration timeout 0
Answered

Hello, We are developing an RF tranceiver using AD9361. We are using a custom board (used ADRV9361 as reference for development) and using No OS software environment. The system works fine with 40 MHz external crystal oscillator to 9361. But due to...

hardware ad9361 Wideband Transceiver IC RF Integrated Transceivers

119 2 0
by HRzhangtao
Design Support AD9361/AD9363/AD9364

Latest 2 days ago by SJagini
35 1 0
Not Answered
AD9631's RX1 and RX2 have Signal spurious 0
Not Answered

When I was using the AD-FMCOMMS3-EBZ evaluation board to r eceive data, I found that the two channels RX1 and RX2 of AD9361 would experience spurious issues under different gain controls without any input signal. There is also a similar problem on the...

hardware zhangtao@cdhuari.com ad9361 Wideband Transceiver IC RF Integrated Transceivers Show More

35 1 0
by roblkc3
Design Support AD9361/AD9363/AD9364

Latest 2 days ago by roblkc3
192 5 0
Not Answered
Frequency offset between input clock and generated signal on FMCOMMS3 0
Not Answered

Hello, I am developing a system that uses as a prototype a ZCU105 with a FMCOMMS3 daughterboard. For my application, I need the generated carrier to be frequency-locked to the reference clock fed into the FMCOMMS3. If I take an Ettus B210 board and...

hardware ad9361 Wideband Transceiver IC ad9361 configuration RF Integrated Transceivers Show More

192 5 0
by kristian
Design Support AD9361/AD9363/AD9364

Latest 3 days ago by SJagini
113 3 0
Not Answered
Gain fluctuation when changing between fast lock profiles and full synthesis 0
Not Answered

We have an application where we're trying to use fast lock profiles to scan across a wide spectrum. We're using manual gain control, with the full table as supplied by analog, and using SPI commands to set the profiles. We calibrate the synthesizer...

software No-os 2019_R1 ad9361 Wideband Transceiver IC RF Integrated Transceivers Show More

113 3 0
by Etobitmis
Design Support AD9361/AD9363/AD9364

Latest 3 days ago by SJagini
55 1 0
Not Answered
RX Channel Amplitude Change with Temperature 0
Not Answered

I am using both of the RX channels to find the relative phase and amplitude. When I use small gains, for example 1dB for RX1 and 7dB for RX2, I read a stable relative amplitude over 20 degrees of temperature change. But if I use high gain for RX1, like...

temperature dependence hardware receiver path ad9361 Wideband Transceiver IC RF Integrated Transceivers Show More

55 1 0
by vargason
Design Support AD9361/AD9363/AD9364

Latest 3 days ago by SJagini
64 1 0
Not Answered
AD9361 MGC pin pulse mode does not lock the gain 0
Not Answered

I am using the MGC pin pulse control mode . After giving a pulse, I don’t see the signal increase within 100 FB_CLK, but the subsequent signal fluctuates in size. Now I don’t understand whether the later increase in the signal is caused by this pulse...

MGC hardware ad9361 Wideband Transceiver IC RF Integrated Transceivers Show More

64 1 0
by IlyaPol
Design Support AD9361/AD9363/AD9364

Latest 3 days ago by SJagini
57 1 0
Not Answered
How to measure TX noise floor 0
Not Answered

Hi, We are working with a custom board with the AD9361 and uses the NO-OS driver. We are investigating an issue related to low-power transmission performance. Problem description: When transmitting 64-QAM at very high attenuation settings (TX attenuation...

hardware noise floor ad9361 Wideband Transceiver IC RF Integrated Transceivers Show More

57 1 0
by Orobin
Design Support AD9361/AD9363/AD9364

Latest 4 days ago by Orobin
116 2 0
Not Answered
ADRV9364-Z7020 Digital tune 0
Not Answered

Hello, I have issues with the ADRV9364-Z7020, the digital tuning on RX and Tx path are not working. I tried using LVDS and CMOS with the associated hardware design I also tried using internal refclk outputed by Y4 XO or injecting an external reference...

software No-Os ad9361 API Wideband Transceiver IC RF Integrated Transceivers

116 2 0
by WindMelody167
Design Support AD9361/AD9363/AD9364

Latest 5 days ago by WindMelody167
145 3 0
Not Answered
An unexpected signal appears when the enable signal transitions from low to high.(TDD mode/AD9361) 0
Not Answered

The ZYNQ7035+AD9361 hardware platform we use employs a self-organizing network protocol optimized for short frames. When using the TDD mode, during the time slot switching period, I first pull the Enable low. After switching the TXNRX, I wait a moment...

hardware ad9361 transmit ad9361 TDD MODE Wideband Transceiver IC RF Integrated Transceivers Show More

145 3 0
by AthosP
Design Support AD9361/AD9363/AD9364

Latest 6 days ago by SJagini
212 3 1
Not Answered
ADALM-PLUTO revC phase between RX1 RX2 is not stable 0
Not Answered

Hi, I am using ADALM-PLUTO revC with RX1 and RX2 enabled as per Pluto Rev C how to activate the 2nd Rx channel I connected a CW source on both RX channels with a splitter and I utilized the ADI IIO OSC software to monitor the received signals. I would...

adalm-pluto hardware Wideband Transceiver IC rf and microwave RF Integrated Transceivers Show More

212 3 1
by Hamima
Design Support AD9361/AD9363/AD9364

Latest 6 days ago by SJagini
191 3 1
Not Answered
FMComms5 phase synchronization for phased array applications 0
Not Answered

Hello, I am currently working with the FMCOMMS5 for phased array experiments. To achieve this, I need phase-coherent signals across all four Tx channels and not only at baseband, but also at the carrier level. I would like to know if this board can provide...

hardware phased array ad9361 sdr fmcomms5 Wideband Transceiver IC RF Integrated Transceivers Show More

191 3 1
by AMRUTH
Design Support AD9361/AD9363/AD9364

Latest 9 days ago by AMRUTH
104 2 0
Not Answered
AD9361 DATA_CLK cannot reach 25 MHz with 50 MHz reference clock 0
Not Answered

I’m working with the AD9361 in a 2Rx/2Tx configuration with a 50 MHz reference clock. My goal is to achieve a DATA_CLK of 25 MHz (or at least 50 MHz), but despite adjusting the RX/TX path clocks and FIR settings, I am only seeing 30 MHz or 60 MHz on the...

NO OS: 2019_R1 software ad9361 AD9361 clocks and interfaces Wideband Transceiver IC RF Integrated Transceivers Show More

104 2 0
by pcr
Design Support AD9361/AD9363/AD9364

Latest 9 days ago by SJagini
72 1 0
Not Answered
Transmitting and Receiving Data Stream 0
Not Answered

We are using two ADALM-Pluto SDRs to communicate and transfer text files. Currently, we are experiencing data loss during single-run transmissions, and we would like to implement a real-time, continuous data stream on both the transmitter and receiver...

adalm-pluto python 3.13.3 pluto sdr software transceiver gnu radio ad9361 data rate qpsk python GNU Radio 3.10.7.0 Wideband Transceiver IC ad9361 configuration rf RF Integrated Transceivers Show More

72 1 0
by ErsinCengiz
Design Support AD9361/AD9363/AD9364

Latest 9 days ago by SJagini
188 5 0
Not Answered
AD9361 – “ad9361_dig_tune_delay: Tuning TX FAILED!” (ZynqMP / Vivado 2021.2, 2Rx-2Tx LVDS) 0
Not Answered

I’m running an AD9361 on a ZynqMP-based design in 2Rx-2Tx (MIMO), LVDS/DDR mode and I’m hitting the following issue: I ran the 1rx1tx mode. It didn't give any errors. When I switched to 2rx2tx mode, I set it to MIMO 1. And then these errors started...

petalinux & vivado 2021.2 software ad9361 Tx tune error Wideband Transceiver IC 2rx-2tx RF Integrated Transceivers Show More

188 5 0
by TANZI7702
Design Support AD9361/AD9363/AD9364

Latest 11 days ago by TANZI7702
127 3 0
Not Answered
band stop filter design 0
Not Answered

hi! I m having trouble to filter out the 1st, 2nd and 3rd harmonics of 433 and 915 MHz. I want to design a band stop filter which suppresses these harmonics, can you suggest me how can I do that, moreoevr, Can i use multiple band stop filters which target...

software fir filter vivado 2019.1 and matlab 2022b ad9361 matlab Wideband Transceiver IC ad9361-z7035 RF Integrated Transceivers Show More

127 3 0

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Answered
AD9361 BBPLL Calibration timeout 0
Answered

Not Answered
AD9631's RX1 and RX2 have Signal spurious 0
Not Answered

Not Answered
Frequency offset between input clock and generated signal on FMCOMMS3 0
Not Answered

Not Answered
Gain fluctuation when changing between fast lock profiles and full synthesis 0
Not Answered

Not Answered
RX Channel Amplitude Change with Temperature 0
Not Answered

Not Answered
AD9361 MGC pin pulse mode does not lock the gain 0
Not Answered

Not Answered
How to measure TX noise floor 0
Not Answered

Not Answered
ADRV9364-Z7020 Digital tune 0
Not Answered

Not Answered
An unexpected signal appears when the enable signal transitions from low to high.(TDD mode/AD9361) 0
Not Answered

Not Answered
ADALM-PLUTO revC phase between RX1 RX2 is not stable 0
Not Answered

Not Answered
FMComms5 phase synchronization for phased array applications 0
Not Answered

Not Answered
AD9361 DATA_CLK cannot reach 25 MHz with 50 MHz reference clock 0
Not Answered

Not Answered
Transmitting and Receiving Data Stream 0
Not Answered

Not Answered
AD9361 – “ad9361_dig_tune_delay: Tuning TX FAILED!” (ZynqMP / Vivado 2021.2, 2Rx-2Tx LVDS) 0
Not Answered

Not Answered
band stop filter design 0
Not Answered

Q&A

Answered AD9361 BBPLL Calibration timeout 0 Answered

Not Answered AD9631's RX1 and RX2 have Signal spurious 0 Not Answered

Not Answered Frequency offset between input clock and generated signal on FMCOMMS3 0 Not Answered

Not Answered Gain fluctuation when changing between fast lock profiles and full synthesis 0 Not Answered

Not Answered RX Channel Amplitude Change with Temperature 0 Not Answered

Not Answered AD9361 MGC pin pulse mode does not lock the gain 0 Not Answered

Not Answered How to measure TX noise floor 0 Not Answered

Not Answered ADRV9364-Z7020 Digital tune 0 Not Answered

Not Answered An unexpected signal appears when the enable signal transitions from low to high.(TDD mode/AD9361) 0 Not Answered

Not Answered ADALM-PLUTO revC phase between RX1 RX2 is not stable 0 Not Answered

Not Answered FMComms5 phase synchronization for phased array applications 0 Not Answered

Not Answered AD9361 DATA_CLK cannot reach 25 MHz with 50 MHz reference clock 0 Not Answered

Not Answered Transmitting and Receiving Data Stream 0 Not Answered

Not Answered AD9361 – “ad9361_dig_tune_delay: Tuning TX FAILED!” (ZynqMP / Vivado 2021.2, 2Rx-2Tx LVDS) 0 Not Answered

Not Answered band stop filter design 0 Not Answered

Answered
AD9361 BBPLL Calibration timeout 0
Answered

Not Answered
AD9631's RX1 and RX2 have Signal spurious 0
Not Answered

Not Answered
Frequency offset between input clock and generated signal on FMCOMMS3 0
Not Answered

Not Answered
Gain fluctuation when changing between fast lock profiles and full synthesis 0
Not Answered

Not Answered
RX Channel Amplitude Change with Temperature 0
Not Answered

Not Answered
AD9361 MGC pin pulse mode does not lock the gain 0
Not Answered

Not Answered
How to measure TX noise floor 0
Not Answered

Not Answered
ADRV9364-Z7020 Digital tune 0
Not Answered

Not Answered
An unexpected signal appears when the enable signal transitions from low to high.(TDD mode/AD9361) 0
Not Answered

Not Answered
ADALM-PLUTO revC phase between RX1 RX2 is not stable 0
Not Answered

Not Answered
FMComms5 phase synchronization for phased array applications 0
Not Answered

Not Answered
AD9361 DATA_CLK cannot reach 25 MHz with 50 MHz reference clock 0
Not Answered

Not Answered
Transmitting and Receiving Data Stream 0
Not Answered

Not Answered
AD9361 – “ad9361_dig_tune_delay: Tuning TX FAILED!” (ZynqMP / Vivado 2021.2, 2Rx-2Tx LVDS) 0
Not Answered

Not Answered
band stop filter design 0
Not Answered