We use the ADRV9026 with a 61.44 MSPS RX sample rate. The ADC sample rate is 1.966 GHz. Hardware is ZCU102+ADRV9026 evaluation board.
We need the RF path delays to be as equal as possible for all inputs. We created a tool to measure the (relative) delays. In our test, we apply a test signal to every input, using a 4-way splitter and matched cables. The splitter and cables are checked with a VNA, the delays are the same within 10's of picoseconds.
When examining the test signal using our calibration software, we see that RX2 and RX3 are always delayed by ~ 1ns with respect to RX1 and RX4. For example, measured delays are 0.0069, 1.0002, 1.0469, 0.0000 for inputs RX1, 2, 3 and 4 (all delays with respect to the shortest one).
This is unexpected. A theory is that the delays are, for some reason, 2 ADC clock cycles delayed for RX2 and RX3? Trace delays alone are not in the 1ns range.
The profile is derived from profile 51-Non-Link-sharing. I tried to enable some additional delays but with no improvement.
Any idea why this is, and if we can improve this?
