Hi,
I have a custom board design with the following:
- two ADRV9029s and an AD9528. The ADRVs have matched SYSREFs and reference clocks and HDL logic uses the same core_clk for the ADRV logic.
- HDL design based on the ADRV9025 reference design at https://github.com/analogdevicesinc/hdl. My project has TX/RX_JESD_M = 16 and TX/RX_JESD_L = 8 so JESD logic is generated for two ADRVs.
- I use the Linux drivers and have based my device-tree based off the ADRV9009-ZUE11G device-tree for the JESD topology
- The board is probing the drivers fine and jesd_status shows 8 lanes up
- validated that the RX IQ looks good on all 8 channels.
- for the 4 channels of a single ADRV, the phase difference between channels is consistent across power-ons
Unfortunately, while I see 4 channels of either one of the ADRVs maintain constant phase differences through power cycles, the two ADRVs are getting a random phase offset between them on a power cycle.
I've searched the forum and am either doing or tried the following:
- set rfPllPhaseSyncMode = 2
- adjusted lmfc offsets - this hasn't made any noticeable difference
I was reading the user guide and it talked about reading register 0x6a8a-0x6a8d to get the elastic buffer depth. One strange thing I noticed is that I can get different values each time I read the registers which seemed strange.
Please make any suggestions of things to look at. I'm pretty confident in the board design as they went above and beyond to make sure of equal length traces and such, and am thinking this is somewhere in the firmware.
Thanks!
