Tx stuck at Link status: WAIT

nQu4n on Apr 20, 2026

Category: Software

Product Number: ADRV9026

Software Version: 2022

Hello,

Our design includes SOM Te0808-9eg and adrv9026. We only use 1 Tx and 3 Rx, so our layout has only 1 JESD lane for Tx and 3 JESD lanes for Rx. Then, when using the Adrv9026 TES software, I realized there's no 3-lane option when creating the profile. Can you confirm if there's another way to run 3 Rx channels with this current design?

For temporary testing, I modified the hdl and profile to run with 1 Tx and 2 Rx. I modified the system_project.tcl file and the profile generated from TES to run with Tx channel 4 (Serdesin D) and Rx 1, 2 (Serdout A and B). I used no-os 2023_R2, and then I logged the Rx status as DATA, however, Tx was stuck at WAIT. Please explain this error to me.

Xilinx Zynq MP First Stage Boot Loader
Release 2022.2 Mar 12 2026 - 16:32:27
PMU-FW is not running, certain applications may not be supported.
adrv9025-phy Rev 0, API version: 6.4.0.14 found
tx_adxcvr: OK (9830400 kHz)
ERR: ../noos/drivers/rf-transceiver/madura/adrv9025.c:26:__adrv9025_dev_err(): adrv9025_jesd204_setup_stage2, 574: failed with TIARx:No solution for RX (3)
rx_adxcvr: OK (9830400 kHz)
ERR: ../noos/drivers/axi_core/jesd204/axi_jesd204_tx.c:697:axi_jesd204_tx_jesd204_link_running(): axi_jesd204_tx_jesd204_link_running: Link0 status failed (WAIT)
WARNING: Link0 deframerStatus 0x13
WARNING: Link2 framerStatus 0x2
adrv9025-phy Rev 176, Firmware 6.4.0.6 API version: 6.4.0.14 Stream version: 9.4.0.1 successfully initialized via jesd204-fsm
tx_jesd status:
Link is enabled
Measured Link Clock: 245.760 MHz
Reported Link Clock: 245.760 MHz
Lane rate: 9830.400 MHz
Lane rate / 40: 245.760 MHz
LMFC rate: 7.680 MHz
SYNC~: deasserted
Link status: WAIT
SYSREF captured: Yes
SYSREF alignment error: No
rx_jesd status:
Link is enabled
Measured Link Clock: 245.760 MHz
Reported Link Clock: 245.760 MHz
Lane rate: 9830.400 MHz
Lane rate / 40: 245.760 MHz
LMFC rate: 7.680 MHz
Link status: DATA
SYSREF captured: Yes
SYSREF alignment error: No
Bye

system_project.tcl:

adrv9026_bd.tcl:

Fullscreen 8004.adrv9026_bd.txt Download

###############################################################################
## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

# TX parameters
set TX_NUM_OF_LANES $ad_project_params(TX_JESD_L)      ; # L
set TX_NUM_OF_CONVERTERS $ad_project_params(TX_JESD_M) ; # M
set TX_SAMPLES_PER_FRAME $ad_project_params(TX_JESD_S) ; # S
set TX_SAMPLE_WIDTH 16                                 ; # N/NP

set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 32 / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)

# RX parameters
set RX_NUM_OF_LANES $ad_project_params(RX_JESD_L)      ; # L
set RX_NUM_OF_CONVERTERS $ad_project_params(RX_JESD_M) ; # M
set RX_SAMPLES_PER_FRAME $ad_project_params(RX_JESD_S) ; # S
set RX_SAMPLE_WIDTH 16                                 ; # N/NP

set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)

set dac_fifo_name axi_adrv9026_dacfifo
set dac_data_width [expr 32*$TX_NUM_OF_LANES]
# set dac_dma_data_width 128
set dac_dma_data_width $dac_data_width

source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl

# adrv9026

create_bd_port -dir I dac_fifo_bypass
create_bd_port -dir I core_clk

# dac peripherals

ad_ip_instance axi_adxcvr axi_adrv9026_tx_xcvr
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.QPLL_ENABLE 1
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.TX_OR_RX_N 1
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.SYS_CLK_SEL 3
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.OUT_CLK_SEL 3

adi_axi_jesd204_tx_create axi_adrv9026_tx_jesd $TX_NUM_OF_LANES

ad_ip_instance util_upack2 util_adrv9026_tx_upack [list \
  NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \
  SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \
  SAMPLE_DATA_WIDTH $TX_SAMPLE_WIDTH \
]

adi_tpl_jesd204_tx_create tx_adrv9026_tpl_core $TX_NUM_OF_LANES \
                                               $TX_NUM_OF_CONVERTERS \
                                               $TX_SAMPLES_PER_FRAME \
                                               $TX_SAMPLE_WIDTH

ad_ip_instance axi_dmac axi_adrv9026_tx_dma
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_TYPE_DEST 1
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.CYCLIC 1
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.ASYNC_CLK_DEST_REQ 1
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.ASYNC_CLK_SRC_DEST 1
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.ASYNC_CLK_REQ_SRC 1
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.MAX_BYTES_PER_BURST 256
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 128
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.FIFO_SIZE 32

ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width

# adc peripherals

ad_ip_instance axi_adxcvr axi_adrv9026_rx_xcvr
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.TX_OR_RX_N 0
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.SYS_CLK_SEL 0
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.OUT_CLK_SEL 3

adi_axi_jesd204_rx_create axi_adrv9026_rx_jesd $RX_NUM_OF_LANES

ad_ip_instance util_cpack2 util_adrv9026_rx_cpack [list \
  NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
  SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
  SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
  ]

adi_tpl_jesd204_rx_create rx_adrv9026_tpl_core $RX_NUM_OF_LANES \
                                               $RX_NUM_OF_CONVERTERS \
                                               $RX_SAMPLES_PER_FRAME \
                                               $RX_SAMPLE_WIDTH

ad_ip_instance axi_dmac axi_adrv9026_rx_dma
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.SYNC_TRANSFER_START 1
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.ASYNC_CLK_DEST_REQ 1
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.ASYNC_CLK_SRC_DEST 1
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.ASYNC_CLK_REQ_SRC 1
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr 32*$RX_NUM_OF_LANES]
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.MAX_BYTES_PER_BURST 256
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.FIFO_SIZE 32

# common cores

ad_ip_instance util_adxcvr util_adrv9026_xcvr
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_RATE 10
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_RATE 10
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_OUT_DIV 1
ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV 4
ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV_4_5 5
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CLK25_DIV 10
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_CLK25_DIV 10
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_PMA_CFG 0x001E7080
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CDR_CFG 0x0b000023ff10400020
ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_FBDIV 40
ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_REFCLK_DIV 1
# ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_INVERT 6
# ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_INVERT 15
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_INVERT 0
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_INVERT 0

# xcvr interfaces

set tx_ref_clk         tx_ref_clk_0
set rx_ref_clk         rx_ref_clk_0

create_bd_port -dir I $tx_ref_clk
create_bd_port -dir I $rx_ref_clk
ad_connect  $sys_cpu_resetn util_adrv9026_xcvr/up_rstn
ad_connect  $sys_cpu_clk util_adrv9026_xcvr/up_clk

# Tx
ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_tx_xcvr axi_adrv9026_tx_jesd {0} core_clk
ad_xcvrpll $tx_ref_clk util_adrv9026_xcvr/qpll_ref_clk_0
ad_xcvrpll axi_adrv9026_tx_xcvr/up_pll_rst util_adrv9026_xcvr/up_qpll_rst_0
ad_xcvrpll $tx_ref_clk util_adrv9026_xcvr/qpll_ref_clk_4
ad_xcvrpll axi_adrv9026_tx_xcvr/up_pll_rst util_adrv9026_xcvr/up_qpll_rst_4

# Rx
ad_xcvrcon  util_adrv9026_xcvr axi_adrv9026_rx_xcvr axi_adrv9026_rx_jesd {} core_clk
for {set i 0} {$i < $RX_NUM_OF_LANES} {incr i} {
  set ch [expr $i]
  ad_xcvrpll  $rx_ref_clk util_adrv9026_xcvr/cpll_ref_clk_$ch
  ad_xcvrpll  axi_adrv9026_rx_xcvr/up_pll_rst util_adrv9026_xcvr/up_cpll_rst_$ch
}

# connections (dac)

ad_connect  core_clk tx_adrv9026_tpl_core/link_clk
ad_connect  axi_adrv9026_tx_jesd/tx_data tx_adrv9026_tpl_core/link

ad_connect  core_clk util_adrv9026_tx_upack/clk
ad_connect  core_clk_rstgen/peripheral_reset util_adrv9026_tx_upack/reset

for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
  ad_connect  tx_adrv9026_tpl_core/dac_enable_$i util_adrv9026_tx_upack/enable_$i
  ad_connect  util_adrv9026_tx_upack/fifo_rd_data_$i tx_adrv9026_tpl_core/dac_data_$i
}

ad_connect  tx_adrv9026_tpl_core/dac_valid_0  util_adrv9026_tx_upack/fifo_rd_en
ad_connect  core_clk axi_adrv9026_dacfifo/dac_clk
ad_connect  core_clk_rstgen/peripheral_reset axi_adrv9026_dacfifo/dac_rst

ad_connect  util_adrv9026_tx_upack/s_axis_valid VCC
ad_connect  util_adrv9026_tx_upack/s_axis_ready axi_adrv9026_dacfifo/dac_valid
ad_connect  util_adrv9026_tx_upack/s_axis_data axi_adrv9026_dacfifo/dac_data

ad_connect  core_clk axi_adrv9026_dacfifo/dma_clk
ad_connect  core_clk_rstgen/peripheral_reset axi_adrv9026_dacfifo/dma_rst
ad_connect  core_clk  axi_adrv9026_tx_dma/m_axis_aclk
ad_connect  axi_adrv9026_dacfifo/dma_valid axi_adrv9026_tx_dma/m_axis_valid
ad_connect  axi_adrv9026_dacfifo/dma_data axi_adrv9026_tx_dma/m_axis_data
ad_connect  axi_adrv9026_dacfifo/dma_ready axi_adrv9026_tx_dma/m_axis_ready
ad_connect  axi_adrv9026_dacfifo/dma_xfer_req axi_adrv9026_tx_dma/m_axis_xfer_req
ad_connect  axi_adrv9026_dacfifo/dma_xfer_last axi_adrv9026_tx_dma/m_axis_last
ad_connect  axi_adrv9026_dacfifo/dac_dunf tx_adrv9026_tpl_core/dac_dunf
ad_connect  axi_adrv9026_dacfifo/bypass dac_fifo_bypass
ad_connect  core_clk_rstgen/peripheral_aresetn axi_adrv9026_tx_dma/m_src_axi_aresetn

# connections (adc)

ad_connect  core_clk rx_adrv9026_tpl_core/link_clk
ad_connect  axi_adrv9026_rx_jesd/rx_sof rx_adrv9026_tpl_core/link_sof
ad_connect  axi_adrv9026_rx_jesd/rx_data_tdata rx_adrv9026_tpl_core/link_data
ad_connect  axi_adrv9026_rx_jesd/rx_data_tvalid rx_adrv9026_tpl_core/link_valid
ad_connect  core_clk util_adrv9026_rx_cpack/clk
ad_connect  core_clk_rstgen/peripheral_reset util_adrv9026_rx_cpack/reset

for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
  ad_connect  rx_adrv9026_tpl_core/adc_enable_$i util_adrv9026_rx_cpack/enable_$i
  ad_connect  rx_adrv9026_tpl_core/adc_data_$i util_adrv9026_rx_cpack/fifo_wr_data_$i
}
ad_connect  $sys_dma_resetn axi_adrv9026_rx_dma/m_dest_axi_aresetn

ad_connect  rx_adrv9026_tpl_core/adc_valid_0 util_adrv9026_rx_cpack/fifo_wr_en
ad_connect  rx_adrv9026_tpl_core/adc_dovf util_adrv9026_rx_cpack/fifo_wr_overflow

ad_connect  core_clk axi_adrv9026_rx_dma/fifo_wr_clk
ad_connect  util_adrv9026_rx_cpack/packed_fifo_wr axi_adrv9026_rx_dma/fifo_wr

# interconnect (cpu)

ad_cpu_interconnect 0x44A00000 rx_adrv9026_tpl_core
ad_cpu_interconnect 0x44A04000 tx_adrv9026_tpl_core
ad_cpu_interconnect 0x44A80000 axi_adrv9026_tx_xcvr
ad_cpu_interconnect 0x44A90000 axi_adrv9026_tx_jesd
ad_cpu_interconnect 0x7c420000 axi_adrv9026_tx_dma
ad_cpu_interconnect 0x44A60000 axi_adrv9026_rx_xcvr
ad_cpu_interconnect 0x44AA0000 axi_adrv9026_rx_jesd
ad_cpu_interconnect 0x7c400000 axi_adrv9026_rx_dma

# gt uses hp0, and 100MHz clock for both DRP and AXI4

ad_mem_hp0_interconnect $sys_cpu_clk sys_ps8/S_AXI_HP0
ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv9026_rx_xcvr/m_axi

# interconnect (mem/dac)

ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect $sys_dma_clk axi_adrv9026_rx_dma/m_dest_axi
ad_mem_hp3_interconnect $sys_dma_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect $sys_dma_clk axi_adrv9026_tx_dma/m_src_axi

# interrupts

ad_cpu_interrupt ps-10 mb-15 axi_adrv9026_tx_jesd/irq
ad_cpu_interrupt ps-11 mb-14 axi_adrv9026_rx_jesd/irq
ad_cpu_interrupt ps-13 mb-12 axi_adrv9026_tx_dma/irq
ad_cpu_interrupt ps-14 mb-11 axi_adrv9026_rx_dma/irq

Profile files:

0726.ActiveUseCase_profile.txt

Fullscreen 2627.ActiveUtilInit_profile.txt Download

const char *json_profile_active_util_init = "{ \n\
  \"radioCtrlInit\": { \n\
    \"radioCtrlModeCfg\": { \n\
      \"txRadioCtrlModeCfg\": { \n\
        \"txEnableMode\": 0, \n\
        \"txChannelMask\": 15 \n\
      }, \n\
      \"rxRadioCtrlModeCfg\": { \n\
        \"rxEnableMode\": 0, \n\
        \"rxChannelMask\": 255 \n\
      }, \n\
      \"orxRadioCtrlModeCfg\": { \n\
        \"orxEnableMode\": 0, \n\
        \"orxPinSelectSettlingDelay_armClkCycles\": 0, \n\
        \"singleChannel1PinModeOrxSel\": 0, \n\
        \"singleChannel2PinModeLowOrxSel\": 0, \n\
        \"singleChannel2PinModeHighOrxSel\": 0, \n\
        \"dualChannel2PinModeOrxSel\": 0 \n\
      } \n\
    }, \n\
    \"txToOrxMapping\": { \n\
      \"orx1Map\": 2, \n\
      \"orx2Map\": 3, \n\
      \"orx3Map\": 2, \n\
      \"orx4Map\": 3 \n\
    }, \n\
    \"streamGpioCfg\": { \n\
      \"streamGpInput0\": 19, \n\
      \"streamGpInput1\": 19, \n\
      \"streamGpInput2\": 19, \n\
      \"streamGpInput3\": 19, \n\
      \"streamGpInput4\": 19, \n\
      \"streamGpInput5\": 19, \n\
      \"streamGpInput6\": 19, \n\
      \"streamGpInput7\": 19, \n\
      \"streamGpInput8\": 19, \n\
      \"streamGpInput9\": 19, \n\
      \"streamGpInput10\": 19, \n\
      \"streamGpInput11\": 19, \n\
      \"streamGpInput12\": 19, \n\
      \"streamGpInput13\": 19, \n\
      \"streamGpInput14\": 19, \n\
      \"streamGpInput15\": 19 \n\
    }, \n\
    \"lo1PllFreq_Hz\": 3500000000, \n\
    \"lo2PllFreq_Hz\": 3550000000, \n\
    \"auxPllFreq_Hz\": 0 \n\
  }, \n\
  \"initCals\": { \n\
    \"calMask\": 862207, \n\
    \"channelMask\": 15, \n\
    \"warmBoot\": 0 \n\
  }, \n\
  \"calRsltsFile\": null, \n\
  \"checkFwVer\": 0 \n\
}\n";

Thread Notes

spopa

on Apr 17, 2026 7:37 AM
0
Hi,

Based on your logs, this is not a standalone TX core issue. The key failure happens earlier in device bring-up:

TIARx: No solution for RX

That indicates the transceiver could not solve the requested RX configuration during PostMcsInit, so later link states are secondary symptoms.

Why you see RX DATA but TX WAIT:
RX and TX are opposite JESD directions. One direction can report DATA while the other remains in WAIT if the overall profile/link setup is inconsistent.

About 1Tx + 3Rx:
In this software/profile flow, the requested 3-Rx operating point is not a supported TES/reference-example configuration. TES not showing that option is expected for unsupported combinations.

Given your setup is custom, we can only support configurations aligned with our reference examples. For debug, please regenerate and keep all of these strictly consistent:

TES profile

HDL lane/channel configuration

no-OS active profile/util init files

If any one of these is out of sync, this exact failure pattern can occur.
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nQu4n on Apr 20, 2026 11:34 AM in reply to spopa
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Hi,
Ignoring the fact that my hardware currently has 1 JESD lane for Tx and 3 lanes for Rx, I have configured HDL to operate with 1 Tx lane and 2 Rx lanes. The no-OS project profile is also configured with 1 Tx and 2 Rx. However, I am still encountering the error shown in my initial log. Please clarify this for me.
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spopa

on Apr 28, 2026 4:43 AM in reply to nQu4n
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Hello,

Your ActiveUseCase_profile.txt still has the full-chip channel masks:

txChannelMask: 15 — all 4 TX channels enabled

rxChannelMask: 255 — all 4 RX + 4 ORx channels enabled

initCals.channelMask: 15 — calibrating all 4 channel pairs

These do not match your reduced 1Tx/2Rx configuration. Regardless of what the HDL and TES profile say, if these masks enable more channels than your JESD links can carry, the API's JESD solver can fail — which is consistent with the TIARx: No solution for RX (3) error you are seeing.

Please make sure the channel masks in this file reflect only the channels you are actually using, and that they are consistent with your TES profile and HDL parameters.
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nQu4n on May 3, 2026 11:35 PM in reply to spopa
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Hello,

This profile i generated using Adrv9026 TES GUI like bellow pictures, please check for me:
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Ramarao

on May 14, 2026 4:36 AM
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You need to manually change the channel mask for the channels that are enabled in your hardware. The GUI by default gives the channel mask for all channels.
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nQu4n on May 14, 2026 6:00 AM in reply to Ramarao
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Hello,

Could you please explain further?

Why isn't the TES GUI updating the channel mask? And if I need to fix it manually, how do I do it?
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vanitha

on May 22, 2026 9:56 AM
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You may need to modify the Rx channel mask and Tx channel mask in the initdata.c and use it for your testing. Please see below as an example.

rxInitChannelMask:
This enables the Rx channels. A decimal value of 17 is 0x11 and will enable Rx1 and ORx1.
Bit[0] = Rx1
Bit[1] = Rx2
Bit[2] = Rx3
Bit[3] = Rx4
Bit[4] = ORx1
Bit[5] = ORx2
Bit[6] = ORx3
Bit[7] = ORx4
Bit[8] = Loopback 1
Bit[9] = Loopback 2

Bit[0] is Tx1 to Bit[3] is Tx4. A value of 3 will enable Tx1 and Tx2.
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