Hi ADI Team,
I am porting the ADRV9029 SDK example to a ZCU102 platform. While I have successfully locked the AD9528 PLL2, I am hitting a critical failure during the BoardProgram phase (Step 7).
Issue Summary: The initialization fails with error 0x12020000 at adi_adrv9025_CpuStartStatusCheck. The CPU status registers consistently return 0x00.
Key Log Snippets:
[1] Chip ID Check: 0x00
[2] Power Status (Reg 0x0018): 0x00
[3] ARM System Status (Reg 0x0080): 0x00
[4] ARM Boot Status (Reg 0x0081): 0x00
...
Error message CpuBootStatus_e: 1 - : CPU is stuck in Powerup mode.
=== ENTERING MAIN ===Step 0: Power Up & Reset (Moved to StaPlatform: Enabling Level Shifters & PVT Power...
HAL_DEBUG: Sysfs GPIO 458 -> 1 OK
Platform: Enabling MGT Power (GPIO 303/304)...
HAL_DEBUG: Sysfs GPIO 303 -> 1 OK
HAL_DEBUG: Sysfs GPIO 304 -> 1 OK
HAL_DEBUG: Sysfs GPIO 470 -> 0 OK
Platform: Performing Hardware Reset (GPIO 480) for AD9528...
HAL_DEBUG: Direct GPIO Write (Pin 480 -> 0, Bank 5, Bit 4) Done.
HAL_DEBUG: Direct GPIO Write (Pin 480 -> 1, Bank 5, Bit 4) Done.
Platform: Performing Hardware Reset (GPIO 469 & 506) for ADRV9025...
HAL_DEBUG: Sysfs GPIO 469 -> 0 OK
HAL_DEBUG: Direct GPIO Write (Pin 506 -> 0, Bank 5, Bit 30) Done.
HAL_DEBUG: Sysfs GPIO 469 -> 1 OK
HAL_DEBUG: Direct GPIO Write (Pin 506 -> 1, Bank 5, Bit 30) Done.
Platform: Waiting 500ms for Boot...
Step 1: Motherboard Discover
INFO: SPI clock frequency successfully set to 5MHz (per User/Kernel requirement).
Step 2: GPIO Enable
Step 2: GPIO Enable
INFO: Skipping Sysfs Clock Check (Driver Unbound). Will configure AD9528 via SPI in Step 6.
Step 3: Daughterboard Discover
Didn't read the entire EEPROM input file /sys/bus/i2c/devices/6-0054/eeprom, it's too long
FRU Version number mismatch 0x38 should be 0x01
WARNING: EEPROM read failed. Forcing ZCU102 Bypass for ADRV9025...
INFO: [Motherboard] Performing Early AD9528 Clock Config...
DEBUG: Ad9528Config Inputs: Dev=245760, VCXO=122880, RefA=30720, FPGA=245760
DEBUG: Config updated for 30.72MHz RefA Input
DEBUG: Config Settings: RefAMode=3 (DIFFERENTIAL), VCXOMode=3 (DIFFERENTIAL)
DEBUG: PLL1 Settings: nDividerPll1=4, re fA_Divider=1
DEBUG: Ad9528Config Success. Using LVDS/Differential mode per device tree.
[HAL] Opening SPI Bus 1 (Fixed Mapping)...
[HAL] Target: /dev/spidev1.1 (CS 1)
[HAL] Skipping Hal-Level Probe (Expect 0x00 due to inactive Clock)...
[HAL] Opening SPI Bus 1 (Fixed Mapping)...
[HAL] Target: /dev/spidev1.0 (CS 0)
[HAL] Skipping Hal-Level Probe (Expect 0x00 due to inactive Clock)...
[HwReset] Performing Hardware Reset (GPIO 469) Count=1...
HAL_DEBUG: Writing GPIO 469 (RESETB) to 0
HAL_DEBUG: Sysfs GPIO 469 -> 0 OK
HAL_DEBUG: Writing GPIO 469 (RESETB) to 1
HAL_DEBUG: Sysfs GPIO 469 -> 1 OK
HAL_DEBUG: Post-Reset Blind Write: Enabling ADRV9025 4-Wire Mode (Reg 0x000 -> 0x18)...
HAL_DEBUG: 4-Wire Mode Enable Sent (3x).
[HwReset] Waiting 50ms for chip boot after reset release...
Step 3 Passed
Step 4: SaveInfo calls
INFO: Rx/Tx InitChannelMask enabled (0x0F). Expecting Gain Table load.
Step 4 Passed
Step 5: Device assignments
Step 5 Passed
Step 6: Clock Configuration
Step 6: Clock Configuration (User Space Init)...
DEBUG: Ad9528Config Inputs: Dev=245760, VCXO=122880, RefA=30720, FPGA=245760
DEBUG: Config updated for 30.72MHz RefA Input
DEBUG: Config Settings: RefAMode=3 (DIFFERENTIAL), VCXOMode=3 (DIFFERENTIAL)
DEBUG: PLL1 Settings: nDividerPll1=4, re fA_Divider=1
DEBUG: Ad9528Config Success. Using LVDS/Differential mode per device tree.
Step 6: Resetting AD9528 (Driver API) ...
HAL_DEBUG: Writing GPIO 480 (RESETB) to 0
HAL_DEBUG: Direct GPIO Write (Pin 480 -> 0, Bank 5, Bit 4) Done.
HAL_DEBUG: Writing GPIO 480 (RESETB) to 1
HAL_DEBUG: Direct GPIO Write (Pin 480 -> 1, Bank 5, Bit 4) Done.
Step 6: Forcing AD9528 into 4-Wire SPI Mode (Reg 0x000 = 0x10)...
Step 6: AD9528 Chip ID (Reg 0x003) = 0x05 (Expected 0x05)
Step 6: Writing Configuration to AD9528 ...
Step 6: PLL Status Check 1/5: Reg 0x508 = 0xE6
PLL1: 0, PLL2: 1, Holdover: 1, VBAT: 1
SUCCESS: AD9528 PLL2 Locked!
Step 6: Enabling Output Channels 1 & 13 (Real Registers 0x501/0x502)....
Step 6: Divider Check (Real Read):
PLL2 N2/AB (0x201) = 0x87
VCO Div (0x204) = 0x03
Ch1 Div (0x305) = 0x04 (Val+1)
Ch13 Div (0x329) = 0x04 (Val+1)
Ch1 Mode (0x304) = 0x40 (Expected 0x40 Boost)
Step 6: Reverting AD9528 to 3-Wire SPI Mode (Freeing MISO)...
Step 6: Post-Revert ID Check (Reg 0x003) = 0x00
SUCCESS: AD9528 MISO Released.
Observation & Questions:
-
SPI / Connectivity: Although the code attempts to set 4-wire mode (Reg 0x000 = 0x18), the Chip ID remains 0x00. Is this indicative of a failed SPI write or a missing Device Clock (DEV_CLK)?
-
AD9528 Transition: My log shows
AD9528 PLL2 Locked, but right after reverting to 3-wire mode, the ID check becomes0x00. Could the MISO line contention be preventing the ADRV9029 from communicating? -
ZCU102 Specifics: Since I am bypassing the official ADS9-based EEPROM check, are there specific GPIOs or power-up sequences (like Level Shifters) on the ZCU102 that need to be held high to enable the ADRV9029 SPI interface?
-
DPD Context: Since I aim to run DPD, is there a known-good reference project for ZCU102 + ADRV9029 that handles the clocking and SPI routing correctly?
I have attached the full console log for your reference. Any insights on why the ARM stays in Powerup mode would be helpful.
Best regards
