Is it appropriate to control (toggle) the TX_EN pin of the ADRV9026 during operation? If TX_EN can be toggled, what limitations or constraints should be considered to avoid losing transmitted (TX) data? For example: Is there a minimum required off-time between two consecutive TX_EN assertions (0 → 1)? When transmitting a short TX burst (e.g. 1 µs of valid TX data), what is the minimum required TX_EN high duration to ensure the data is not lost or truncated? Any guidance on recommended timing or usage of TX_EN for short-burst or TDD-style transmission on the ADRV9026 would be appreciated.

Q&A ADRV9026 TX_EN behavior and TX datapath latency

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ADRV9026 Recommended for New Designs
The ADRV9026 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation...
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ADRV9026 TX_EN behavior and TX datapath latency

RFtransceiver1

on Jan 23, 2026

Category: Datasheet/Specs

Product Number: ADRV9026

Is it appropriate to control (toggle) the TX_EN pin of the ADRV9026 during operation?

If TX_EN can be toggled, what limitations or constraints should be considered to avoid losing transmitted (TX) data?

For example:

Is there a minimum required off-time between two consecutive TX_EN assertions (0 → 1)?
When transmitting a short TX burst (e.g. 1 µs of valid TX data), what is the minimum required TX_EN high duration to ensure the data is not lost or truncated?

Any guidance on recommended timing or usage of TX_EN for short-burst or TDD-style transmission on the ADRV9026 would be appreciated.

Ramarao

on Jan 24, 2026 9:44 AM
0
It is recommended to use PIN mode in case of TDD applications. We use stream processor which is a kind of small microprocessor that does not interact with the internal ARM and enables the TX/RX and ORX channels without any latency. 10us is the minimum width that we would expect on the enable signals.
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RFtransceiver1
on Jan 27, 2026 8:46 AM in reply to Ramarao
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Thanks for your response.

In addition, we are using ADRV9026 in a TDD application with TX controlled by the TX_ENB pin.

Configuration:

TX_ENB width = 2 µs

TX data length = 1 µs

PRI = 20 µs

With this setup, TX pulses are periodically missing (repeating pattern).

Increasing PRI improves the behavior, and at PRI = 32 µs the issue disappears.
If TX_ENB is held high continuously, no TX pulses are missing.

Is this expected behavior due to TX_ENB being too short or TX_ENB-to-valid-data timing?
Could this issue also be caused by other internal limitations, such as TX datapath latency, frame alignment, or stream processor timing in the ADRV9026?
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Ramarao

on Feb 2, 2026 7:45 AM in reply to RFtransceiver1
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The min. TX Enable PIN width must be 10us as specified in the datasheet which is not followed here. What is PRI that you shown above?
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RFtransceiver1
on Feb 2, 2026 10:16 PM in reply to Ramarao
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Thank you for your response.

We have increased the TX_ENB high duration to 10 µs, however the observed behavior remains unchanged.

The PRI we mentioned refers to the Pulse Repetition Interval.

We would appreciate any further clarification or guidance on this issue.
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Ramarao

on Feb 3, 2026 6:00 AM in reply to RFtransceiver1
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Which profile are you using? Are you enabling CFR? If you enable CFR, the Tx path latency will be much higher than 2us.

What is your setup? Is it EVB or custom board?
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RFtransceiver1
on Feb 4, 2026 11:09 AM in reply to Ramarao
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We use custom board.

What is the CFR that you mentioned above ?
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Ramarao

on Feb 8, 2026 1:18 AM in reply to RFtransceiver1
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CFR means crest factor reduction which can impact the TX path latency.
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