Hi AD support,
I design a custom board with FPGA and ADRV9026. I can drive ADRV9026 in 13-nonLinkshare and 51-nonlinkshare profile table correctly and rx_Sync and tx_sync are settled to '1' in rx and tx bringing up.
Now, I want to drive ADRV9026 with 88-linkshare profile table. but I have a problem with that.
as you can see in profile table serdes lane rate is 14.7456 Gbps but in 13-nonLinkshare and 51-nonlinkshare profile table serdes lane rate is 9.8304 Gbps.
when I bring up rx and tx, tx_sync and rx_sync not settle to '1' and chang between '1' and '0'. you can see these signals in vivado chipscope in the figure below.
I set F = 3 and K = 32 in JESD IP in Xilinx IP as mention in version 6.4.0.17 of GUI version in demo mode.
can you help me for this bug?
In initdata.c, deviceClock_kHz = 245760, clkPllVcoFreq_kHz = 9830400 and serdesPllVcoFreq_kHz = 14745600. what is the difference between clkPllVcoFreq_kHz and serdesPllVcoFreq_kHz? and why clkPllVcoFreq_kHz isn't 14745600?
In 13-nonLinkshare and 51-nonlinkshare profile table serdesPllVcoFreq_kHz = 0 and clkPllVcoFreq_kHz = Serdes lane rate = 9830400 .
In FPGA I set lane rate = 14745600 Kbps and QPLL clock = 245.76 MHz and FPGA Global clk for JESD link = 491.52 M.
Also I use adi_daughterboard_ClockConfig(motherboard->daughterboards[0], (uintptr_t) &ad9528InitInst, 245760, 122880, 122880, 491520); function for generate clock from AD9528 for 88-linkshare profile table.
In 13-nonLinkshare and 51-nonlinkshare profile table, I use adi_daughterboard_ClockConfig(motherboard->daughterboards[0], (uintptr_t) &ad9528InitInst, 245760, 122880, 122880, 245760); function.
As an other question, Can I achieve real time 300 M Rx bandwidth and 450 M Tx bandwidth with 88-linkshare profile table?
