Latency

Minimum Pulse width for the TX enable, RX enable and ORX enable signals.

Michaelp3 said:

TXx_EN Pulse Width

RXx_EN Pulse Width

ORX_CTRL_x Pulse Width

Michaelp3 said:

TXx_EN to Valid Data

RXx_EN to Valid Data

ORX_CTRL_x to Valid Data

Latency required for the valid data to come out of the TRx. For eg, 2us is the latency for the Tx data to come out of Tx output path.

The latency depends on the Use case and the JESD latency will be maintained by using SYSREF.

Hi Ramarao thanks for the reply!

What are the use cases that can change the latency? is there any tolerance?

We wish to operate this transceiver in radar system and constant latency is crucial for us. 

Please share the profile that you are using, we would be able to provide you with the latency details.

I'd like to operate in FDD mode when both Rx and Tx PLLs are with the same frequency.

Constant gain mode (MGC).

4 Tx. and 4 Rx channels enabled.

16bit ADC.

center frequency ~3GHz.

In general, we plan to use this transceiver in radar system where we transmit 0.9usec pulse with PRI of 2 to 10usec.

In the GUI, there are multiple profiles that you can select from. Please let me know which profile are you trying to use.

I don't have the transceiver yet.

Let's go with:

TX BW: the minimum there is, say 100MHz

Tx input rate 122.88MHz

Tx DAC rate 1.966GHz

ORX BW 100MHz

ORX Output rate 245.76MHz

ORX ADC rate 4.915GHz

RX BW 100MHz

RX output rate 122.88MHz

Rx ADC rate 1.966GHz

JESD 16

thanks,

Herewith, im providing the latency values for 50 NLS profile.

Tx Latency is 34.25 samples or 279ns. If you enable CFR, this will change drastically.

Rx Latency is 97.75 samples or 795ns

JESD deterministic latency will be maintained by using SYSREF.

Thanks.

Deterministic latency means that it will be constant during operation by SYSREF? Can it vary by temperature? How much?

It might vary but the elastic buffers with in TRX would take care of the variation.