DPD on ADRV9029 ISSUE

Hi Yashar,

The Ref. Clock input depends on the profile that you are using. Every profile will have defined its Ref. clock and you need to use that accordingly. If you want to customise a Ref.clock for an Use case, that is possible.

In any case, the Ref.clock must be a multiple of the TX/RX IQ sampling rates.

Coming to DPD issue, what is the exact problem?

Are you not getting expected ACLR? Or the DPD itself is not running? Which model are you using?

What is your PA lineup? Can you share the DPD statistics and DPD tracking configuration settings.

If you can share more data, i will be able to get back with specifics.

Hi officer

thanks for your reply. regadring clock rate, i always apply external clock to J6 port of daugter board as 122.88MHz. when i change the external clock generator's frequency to for instance 245.76MhZ PLL doesnt lock. and i can not program it. shall i always apply 122.88MHz to J6? i laso have a question about different profiles, when i load a profile it should automatically change the REF A clock , VCXO clock device clock frequency?! 

about DPD, i want to apply DPD for 160 MHz BW signal but I cant get good answer. is it posible to help me which profile i should use and how i should change the settings of ADI GUI to have it working?! i can apply DPD with lower BW to the same device but when i apply 160 MHz it doesnt have any results. 

also sometimes when i am applying all steps as mentioned in manual to do DPD it doenst change any thing and it gives me DPD stability error, how should i avoid that?

Yashar said:

thanks for your reply. regadring clock rate, i always apply external clock to J6 port of daugter board as 122.88MHz. when i change the external clock generator's frequency to for instance 245.76MhZ PLL doesnt lock. and i can not program it. shall i always apply 122.88MHz to J6? i laso have a question about different profiles, when i load a profile it should automatically change the REF A clock , VCXO clock device clock frequency?! 

I just checked all the profiles and we seem to have all the profiles with Ref clock as 122.88MHz. If you need other than , for eg, 245.76MHz, you need to customize and then program with the modified profile.

Go through the link for more details.

 RE: Few Questions about demo mode of Evaluation sofeware 6.4.0.17 

Is there any specific reason why do you want to use Ref. clock other than 122.88MHz?

Since your signal BW is 160MHz, you need to use any profile with 245.76MSPS which can be UC51.

Can you please share raw ACLR, CCDF plots without DPD and share ACLR and CCDF plots after enabling DPD?

Looks like you are not using CFR which may be required to better operate the PA at little higher powers so the PA wont be compressing.

Hi Ramaro

many thanks for your reply. i want to increase ORx and Tx sample rate because, my desired signals BW is 160 MHz (2x80MHz) so the ORx port should be capable enought to cover the 160 MHz (80 MHz wanted signal+80 MHz adjacent channel). to do this ORx and Tx ports should have at least 320 Msps SAMPLE RATE. therefore i need to load those profile which have higher clock rate and sample rate. but unfortunately when i am applyinh 122.88 MHz signal as external clock to J613 and load the profile with 491.52 MHz, sample rate, Tx generate the unrelevent signal. so my question is when i am loading a profile with 491.52MHz sample rate shall i apply the same clock to J613?! OR NOT?!

and about CFR and aclr results before and after DPD with 160 MHz BW signal, i uploaded them results. in both condition CFR is 8.7 dB . However if you look at DPD results adjacent channel power is rising over frequency ( it should not be like this) so this is the reason which i think i have to apply higher sample rate correctly. would you please let me know how should i do that?!

also did you try DPD with signal with more than 160 MHz BW on a dut, ? is it possible to share your instruction and config files with me so i can ensure i am doing right thing here?!

the first two plots are after DPD

 and the last two before DPD

Yashar said:

many thanks for your reply. i want to increase ORx and Tx sample rate because, my desired signals BW is 160 MHz (2x80MHz) so the ORx port should be capable enought to cover the 160 MHz (80 MHz wanted signal+80 MHz adjacent channel). to do this ORx and Tx ports should have at least 320 Msps SAMPLE RATE. therefore i need to load those profile which have higher clock rate and sample rate. but unfortunately when i am applyinh 122.88 MHz signal as external clock to J613 and load the profile with 491.52 MHz, sample rate, Tx generate the unrelevent signal. so my question is when i am loading a profile with 491.52MHz sample rate shall i apply the same clock to J613?! OR NOT?!

For your carrier configuration, UC51 will be fine and please test with UC51 with Ref clock of 122.88MHz.

Yashar said:

and about CFR and aclr results before and after DPD with 160 MHz BW signal, i uploaded them results. in both condition CFR is 8.7 dB . However if you look at DPD results adjacent channel power is rising over frequency ( it should not be like this) so this is the reason which i think i have to apply higher sample rate correctly. would you please let me know how should i do that?!

No, Please use UC51 which will work fine.

Yashar said:

also did you try DPD with signal with more than 160 MHz BW on a dut, ? is it possible to share your instruction and config files with me so i can ensure i am doing right thing here?!

Yes, we did. The Tranceiver supports TX RF bandwidth of 200MHz with DPD.

Please go through the PA reports in the below link for your reference.

 Power Amplifier Test Reports 

what do you mean "51UC"? You mean using profile 51 nonlink sharing profile should work?! is there any special DPD setting recommended to change to apply 160MHz BW for DPD?!

UC51 means Use Case 51. Either you can use Link Sharing or Non Link Sharing.

No, we dont need to have special DPD setting other than optimizing the DPD Tracking configuration parameters.

UC 51 only has 245.76 MHz sample rate for ORx port. so it is not enough for applying DPD with 160 MHz signal. i think i  need sample rate more than 2x160MHz=320MHz TO HAVE CORRECT MEASUREMENT. and when i am using UCs with 451.92MHz sample rate, Tx doesnt generate right signal at all. would you please help us to sort this prob;em out? it is essential for us.

Please use UC51, it has ORX BW of 450MHz. Are you facing any issue with UC51 when you try to test DPD?

To add, Sampling rate and ADC rates are not same. We have intepolations inside and for UC51 ADC is running at ~4.9 GHz.