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ADRV9029: Rx is stuck in the CGS stage during JESD 204B initialization.

Category: Software
Product Number: ADTV9029
Software Version: 6.4.0.17

The platform we are using is ZC706+ADRV9026-MB/PCBZ (sub board), and the corresponding software version is 6.4.0.17。

We have made modifications to the FPFA project of ZC706+ADRV9009 and replaced the FPGA related code in ADRV9029 with the FPGA related code in ADRV9009 sdk.

The polarity of SYNCIN, SERDOUT, and SERDIN is processed in the FPGA to ensure that there are no issues.

In the process of building JESD204B, the SYNC signal has been unable to pull up. Keeping track of the states of deframer and framer gives the following:

Deframer status = 0x12; Framer status = 0x02;

1. The FPGA RX terminal pulls down the SYNC signal and sends it to ADRV9029, but the data received by the RX from ADRV9029 is not K28.5, as shown in the following figure:

Using adi_Adrv9025_FramerStatusGet(), the return value obtained is:framerSel:1--status:2-framerSyncNeCount:1--qbfStateStatus:0--syncNSel:0--

Why is the data sent by ADRV9029 not K28.5(0xbc)?

2.The FPGA TX end received a SYNC signal that was pulled low, and the TX end had already sent K28.5 to ADRV9029. However, ADRV9029 did not pull up the SYNC signal.

Using adi_adrv9025_DeframerStatusGet(), the return value obtained is:deframerSel:1--status:0x12--

3. In adi_ Board_ Adrv9025_ Default ADI in JesdTxBridgup()_ ADRV9025_ SERDES_ INIT detection, return message is' error: SERDES: Lane is powered down '.

Using adi_adrv9025_DfrmLinkConditionGet() Get ADI_ADRV9025_DEFRAMER_0,return 0. 

I didn't modify the calls in the SDK, just re implemented the FPGA code in the SDK. May I ask, what is the reason for the above results?

This is the parameter for JESD 204B in the relevant file I used (using 13_nonLinkSharing to generate the corresponding main. c and inidata. c):

{ // dataInterface
{ // framer (array)
{ // framer[0]
0, // enableJesd204C
0, // bankId
1, // deviceId
0, // lane0Id
8, // jesd204M
32, // jesd204K
8, // jesd204F
16, // jesd204Np
0, // jesd204E
1, // scramble
3, // serializerLanesEnabled
0, // lmfcOffset
0, // syncbInSelect
0, // overSample
1, // syncbInLvdsMode
0, // syncbInLvdsPnInvert
{ // serializerLaneCrossbar
0, // lane0FramerOutSel
1, // lane1FramerOutSel
8, // lane2FramerOutSel
8 // lane3FramerOutSel
},
{ // adcCrossbar
ADI_ADRV9025_ADC_RX1_I, // conv0
ADI_ADRV9025_ADC_RX1_Q, // conv1
ADI_ADRV9025_ADC_RX2_I, // conv2
ADI_ADRV9025_ADC_RX2_Q, // conv3
ADI_ADRV9025_ADC_DUALBAND_RX3_BAND_A_I, // conv4
ADI_ADRV9025_ADC_RX3_Q, // conv5
ADI_ADRV9025_ADC_DUALBAND_RX4_BAND_A_I, // conv6
ADI_ADRV9025_ADC_RX4_Q, // conv7
ADI_ADRV9025_ADC_DISABLE, // conv8
ADI_ADRV9025_ADC_DISABLE, // conv9
ADI_ADRV9025_ADC_DISABLE, // conv10
ADI_ADRV9025_ADC_DISABLE, // conv11
ADI_ADRV9025_ADC_DISABLE, // conv12
ADI_ADRV9025_ADC_DISABLE, // conv13
ADI_ADRV9025_ADC_DISABLE, // conv14
ADI_ADRV9025_ADC_DISABLE, // conv15
ADI_ADRV9025_ADC_DISABLE, // conv16
ADI_ADRV9025_ADC_DISABLE, // conv17
ADI_ADRV9025_ADC_DISABLE, // conv18
ADI_ADRV9025_ADC_DISABLE, // conv19
ADI_ADRV9025_ADC_DISABLE, // conv20
ADI_ADRV9025_ADC_DISABLE, // conv21
ADI_ADRV9025_ADC_DISABLE, // conv22
ADI_ADRV9025_ADC_DISABLE // conv23
},
0, // newSysrefOnRelink
0, // sysrefForStartup
0, // sysrefNShotEnable
0, // sysrefNShotCount
0 // sysrefIgnoreWhenLinked
},
{ // framer[1]
0, // enableJesd204C
0, // bankId
0, // deviceId
0, // lane0Id
0, // jesd204M
0, // jesd204K
0, // jesd204F
0, // jesd204Np
0, // jesd204E
0, // scramble
0, // serializerLanesEnabled
0, // lmfcOffset
1, // syncbInSelect
0, // overSample
1, // syncbInLvdsMode
0, // syncbInLvdsPnInvert
{ // serializerLaneCrossbar
0, // lane0FramerOutSel
0, // lane1FramerOutSel
0, // lane2FramerOutSel
0 // lane3FramerOutSel
},
{ // adcCrossbar
ADI_ADRV9025_ADC_DISABLE, // conv0
ADI_ADRV9025_ADC_DISABLE, // conv1
ADI_ADRV9025_ADC_DISABLE, // conv2
ADI_ADRV9025_ADC_DISABLE, // conv3
ADI_ADRV9025_ADC_DISABLE, // conv4
ADI_ADRV9025_ADC_DISABLE, // conv5
ADI_ADRV9025_ADC_DISABLE, // conv6
ADI_ADRV9025_ADC_DISABLE, // conv7
ADI_ADRV9025_ADC_DISABLE, // conv8
ADI_ADRV9025_ADC_DISABLE, // conv9
ADI_ADRV9025_ADC_DISABLE, // conv10
ADI_ADRV9025_ADC_DISABLE, // conv11
ADI_ADRV9025_ADC_DISABLE, // conv12
ADI_ADRV9025_ADC_DISABLE, // conv13
ADI_ADRV9025_ADC_DISABLE, // conv14
ADI_ADRV9025_ADC_DISABLE, // conv15
ADI_ADRV9025_ADC_DISABLE, // conv16
ADI_ADRV9025_ADC_DISABLE, // conv17
ADI_ADRV9025_ADC_DISABLE, // conv18
ADI_ADRV9025_ADC_DISABLE, // conv19
ADI_ADRV9025_ADC_DISABLE, // conv20
ADI_ADRV9025_ADC_DISABLE, // conv21
ADI_ADRV9025_ADC_DISABLE, // conv22
ADI_ADRV9025_ADC_DISABLE // conv23
},
0, // newSysrefOnRelink
0, // sysrefForStartup
0, // sysrefNShotEnable
0, // sysrefNShotCount
0 // sysrefIgnoreWhenLinked
},
{ // framer[2]
0, // enableJesd204C
0, // bankId
0, // deviceId
0, // lane0Id
0, // jesd204M
0, // jesd204K
0, // jesd204F
0, // jesd204Np
0, // jesd204E
0, // scramble
0, // serializerLanesEnabled
0, // lmfcOffset
0, // syncbInSelect
0, // overSample
0, // syncbInLvdsMode
0, // syncbInLvdsPnInvert
{ // serializerLaneCrossbar
0, // lane0FramerOutSel
0, // lane1FramerOutSel
0, // lane2FramerOutSel
0 // lane3FramerOutSel
},
{ // adcCrossbar
ADI_ADRV9025_ADC_DISABLE, // conv0
ADI_ADRV9025_ADC_DISABLE, // conv1
ADI_ADRV9025_ADC_DISABLE, // conv2
ADI_ADRV9025_ADC_DISABLE, // conv3
ADI_ADRV9025_ADC_DISABLE, // conv4
ADI_ADRV9025_ADC_DISABLE, // conv5
ADI_ADRV9025_ADC_DISABLE, // conv6
ADI_ADRV9025_ADC_DISABLE, // conv7
ADI_ADRV9025_ADC_DISABLE, // conv8
ADI_ADRV9025_ADC_DISABLE, // conv9
ADI_ADRV9025_ADC_DISABLE, // conv10
ADI_ADRV9025_ADC_DISABLE, // conv11
ADI_ADRV9025_ADC_DISABLE, // conv12
ADI_ADRV9025_ADC_DISABLE, // conv13
ADI_ADRV9025_ADC_DISABLE, // conv14
ADI_ADRV9025_ADC_DISABLE, // conv15
ADI_ADRV9025_ADC_DISABLE, // conv16
ADI_ADRV9025_ADC_DISABLE, // conv17
ADI_ADRV9025_ADC_DISABLE, // conv18
ADI_ADRV9025_ADC_DISABLE, // conv19
ADI_ADRV9025_ADC_DISABLE, // conv20
ADI_ADRV9025_ADC_DISABLE, // conv21
ADI_ADRV9025_ADC_DISABLE, // conv22
ADI_ADRV9025_ADC_DISABLE // conv23
},
0, // newSysrefOnRelink
0, // sysrefForStartup
0, // sysrefNShotEnable
0, // sysrefNShotCount
0 // sysrefIgnoreWhenLinked
}
}, // framer (end of array)
{ // deframer (array)
{ // deframer[0]
0, // enableJesd204C
0, // bankId
1, // deviceId
0, // lane0Id
8, // jesd204M
32, // jesd204K
4, // jesd204F
16, // jesd204Np
0, // jesd204E
1, // scramble
15, // deserializerLanesEnabled
0, // lmfcOffset
0, // syncbOutSelect
1, // syncbOutLvdsMode
0, // syncbOutLvdsPnInvert
0, // syncbOutCmosSlewRate
0, // syncbOutCmosDriveLevel
{ // deserializerLaneCrossbar
0, // deframerInput0LaneSel
1, // deframerInput1LaneSel
2, // deframerInput2LaneSel
3 // deframerInput3LaneSel
},
{ // dacCrossbar
ADI_ADRV9025_DEFRAMER_OUT0, // tx1DacChanI
ADI_ADRV9025_DEFRAMER_OUT1, // tx1DacChanQ
ADI_ADRV9025_DEFRAMER_OUT2, // tx2DacChanI
ADI_ADRV9025_DEFRAMER_OUT3, // tx2DacChanQ
ADI_ADRV9025_DEFRAMER_OUT4, // tx3DacChanI
ADI_ADRV9025_DEFRAMER_OUT5, // tx3DacChanQ
ADI_ADRV9025_DEFRAMER_OUT6, // tx4DacChanI
ADI_ADRV9025_DEFRAMER_OUT7 // tx4DacChanQ
},
0, // newSysrefOnRelink
1, // sysrefForStartup
0, // sysrefNShotEnable
0, // sysrefNShotCount
0 // sysrefIgnoreWhenLinked
},
{ // deframer[1]
0, // enableJesd204C
0, // bankId
0, // deviceId
0, // lane0Id
0, // jesd204M
0, // jesd204K
0, // jesd204F
0, // jesd204Np
0, // jesd204E
0, // scramble
0, // deserializerLanesEnabled
0, // lmfcOffset
0, // syncbOutSelect
0, // syncbOutLvdsMode
0, // syncbOutLvdsPnInvert
0, // syncbOutCmosSlewRate
0, // syncbOutCmosDriveLevel
{ // deserializerLaneCrossbar
8, // deframerInput0LaneSel
8, // deframerInput1LaneSel
8, // deframerInput2LaneSel
8 // deframerInput3LaneSel
},
{ // dacCrossbar
ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx1DacChanI
ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx1DacChanQ
ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx2DacChanI
ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx2DacChanQ
ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanI
ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx3DacChanQ
ADI_ADRV9025_DEFRAMER_OUT_DISABLE, // tx4DacChanI
ADI_ADRV9025_DEFRAMER_OUT_DISABLE // tx4DacChanQ
},
0, // newSysrefOnRelink
0, // sysrefForStartup
0, // sysrefNShotEnable
0, // sysrefNShotCount
0 // sysrefIgnoreWhenLinked
}
}, // deframer (end of array)
{ // serCfg (array)
{ // serCfg[0]
0, // serAmplitude
1, // serPreEmphasis
3, // serPostEmphasis
0 // serInvertLanePolarity
},
{ // serCfg[1]
0, // serAmplitude
1, // serPreEmphasis
3, // serPostEmphasis
0 // serInvertLanePolarity
},
{ // serCfg[2]
0, // serAmplitude
1, // serPreEmphasis
3, // serPostEmphasis
0 // serInvertLanePolarity
},
{ // serCfg[3]
0, // serAmplitude
1, // serPreEmphasis
3, // serPostEmphasis
0 // serInvertLanePolarity
}
}, // serCfg (end of array)
{ // desCfg (array)
{ // desCfg[0]
0, // desInvertLanePolarity
0, // highBoost
0, // configOption1
0, // configOption2
0, // configOption3
0, // configOption4
0, // configOption5
0, // configOption6
0, // configOption7
0, // configOption8
0, // configOption9
0 // configOption10
},
{ // desCfg[1]
0, // desInvertLanePolarity
0, // highBoost
0, // configOption1
0, // configOption2
0, // configOption3
0, // configOption4
0, // configOption5
0, // configOption6
0, // configOption7
0, // configOption8
0, // configOption9
0 // configOption10
},
{ // desCfg[2]
0, // desInvertLanePolarity
0, // highBoost
0, // configOption1
0, // configOption2
0, // configOption3
0, // configOption4
0, // configOption5
0, // configOption6
0, // configOption7
0, // configOption8
0, // configOption9
0 // configOption10
},
{ // desCfg[3]
0, // desInvertLanePolarity
0, // highBoost
0, // configOption1
0, // configOption2
0, // configOption3
0, // configOption4
0, // configOption5
0, // configOption6
0, // configOption7
0, // configOption8
0, // configOption9
0 // configOption10
}
}, // desCfg (end of array)
{ // linkSharingCfg
0, // linkSharingEnabled
0, // linkSharingM
1, // linkSharingS
0, // linkSharingNp
{ // linkSharingAdcCrossbar
ADI_ADRV9025_ADC_DISABLE, // conv0
ADI_ADRV9025_ADC_DISABLE, // conv1
ADI_ADRV9025_ADC_DISABLE, // conv2
ADI_ADRV9025_ADC_DISABLE, // conv3
ADI_ADRV9025_ADC_DISABLE, // conv4
ADI_ADRV9025_ADC_DISABLE, // conv5
ADI_ADRV9025_ADC_DISABLE, // conv6
ADI_ADRV9025_ADC_DISABLE, // conv7
ADI_ADRV9025_ADC_DISABLE, // conv8
ADI_ADRV9025_ADC_DISABLE, // conv9
ADI_ADRV9025_ADC_DISABLE, // conv10
ADI_ADRV9025_ADC_DISABLE, // conv11
ADI_ADRV9025_ADC_DISABLE, // conv12
ADI_ADRV9025_ADC_DISABLE, // conv13
ADI_ADRV9025_ADC_DISABLE, // conv14
ADI_ADRV9025_ADC_DISABLE // conv15
},
},
{ // dataCfg
0, // enable
0, // configOption1
0 // configOption2
},
0, // channelSelect
0 // channelMode
}

  • Refer to the below link for  the JESD debugging document.

     https://ez.analog.com/rf/wide-band-rf-transceivers/design-support-ad9371/w/documents/13976/jesd-debugging

    From the status of SYNC signal , seems its always low so its stuck in CGS phase . Go through the debugging steps provided in the document shared and see if the issue is resolved .

    From the log you have shared seems the deframer and framer status is 0x12 and 0x2 which is  incorrect ,it  should be 0x87 and 0xA respectively 

    From the deframer status it indicates FS Lost error (framing error).

    This can be caused by :

    -> Excessive intra lane skew. For this can you try using single lane and see if you don't see issue .

    -> Polarity of one or more lanes is inverted. 

    Can you check the lane parameters mismatch  between framer and deframer using adi_adrv9025_DfrmIlasMismatchGet() API.

  • Hi,Ramarao:

    I would like to ask, what is the reason why the data sent by ADRV9029 to FPGA is not K28.5(0xBC))?

  •  Have you tried testing the signal integrity of the lanes using PRBS generator and PRBS  checker present in the chip. 

  • Hi,vabitha

      JESD 204B is in the CGS stage and can be used RX Framer PRBS generatior?
    If I use:
       frmTestDataCfg.framerSelMask =ADI_ADRV9025_FRAMER_0;
       frmTestDataCfg.testDataSource = ADI_ADRV9025_FTD_PRBS7;
       frmTestDataCfg.injectPoint = ADI_ADRV9025_FTD_FRAMERINPUT;
       adi_adrv9025_FramerTestDataSet(adrv9025_device,&frmTestDataCfg);
    How to obtain test results? Is it tracking data on FPGA?

  • Please use the below injection point for the framer data configuration as Serializer  . 

    FrmTestDataCfg.injectPoint=Types.adi_adrv9025_FramerDataInjectPoint_e.ADI_ADRV9025_FTD_SERIALIZER

    Give same PRBS test pattern for both FPGA and TRX  and you shouldn't see any errors in this case . And also try with different test patterns For example , PRBS 7 for TRX and PRBS 15 for FPGA and in this case you should see errors .

    The valid test patterns are 1:PRBS7; 2:PRBS9; 3:PRBS15; 5:PRBS31.

  • The motherboard I used was not the ADS9, and the FPGA project I used was not provided by ADI. I modified it for the FPGA project of ADRV9009. Therefore, there are no RPBS-related test procedures in FPGas. Is there another way to verify or fix the problem I'm having? Does the ADRV9029 itself have an associated test interface or corresponding register?

  • I use adi_ Adrv9025_ DfrmIlasMismatchGet() obtains information for ADI_ADRV9025_DEFRAMER_0, and the result shows that zeroCheckFlag is 0, indicating that the DeframerA connection is not activated. I think this is normal. Because from the FPGA tracking results, it can be seen that the FPGA has been sending K28.5 data to ADRV9029, but ADRV9029 has not set SYNCOUT to high。
    So Tx JESD 204B should always be in the CGS stage。

    How do I know if each channel of ADRV9029 has received K28.5?Can you provide a corresponding function interface or register interface to obtain the corresponding status from within ADRV9029?

  • Please refer to UG-1727 section for more details on debug "LINK INITIALIZATION AND DEBUGGING".

    From UG-1727,

    If stuck in CGS mode, or if SYNC stays at logic low level or pulses high for less than four multiframes, take the following steps:
    1. Check the board, unpowered for the following:

    a. SYSREF and SYNC signaling is dc-coupled.

    b. Check that the pull-down or pull-up resistors are not dominating the signaling, for example if values are too small or shorted
    and therefore cannot be driven correctly.

    c. Verify that the differential-pairs traces are length matched.

    d. Verify differential impedance of the traces is 100 Ω.

    2. Check the board, powered:

    a. If there is a buffer/translator in the SYNC path, make sure it is functioning properly.

    b. Check that SYNC source is properly configured to produce compliant logic levels.


    3. Check SYNC signaling:

            a. If SYNC is static and logic low, the link is not progressing beyond the CGS phase. There is either an issue with the data being sent or the JESD204 receiver is not decoding the samples properly. Verify /K/ characters are being sent, verify receive configuration settings, verify SYNC source. Consider overdriving SYNC signal and attempt to force link into ILAS mode to isolate link Rx vs. Tx issues.

    b. If SYNC is static and logic high, verify the SYNC logic level is configured correctly in the source device. Check pull-up and pull-down resistors.

    c. If SYNC pulses high and returns to logic-low state for less than six multiframe periods, the JESD204 Link is progressing beyond the CGS phase but not beyond ILAS phase. This suggests the /K/ characters are okay and the basic function of the CDR are working. Proceed to ILAS troubleshooting.

    d. If SYNC pulses high for a duration of more than six multiframe periods, the Link is progressing beyond the ILAS phase and is malfunctioning in the data phase; see the data phase section for troubleshooting tips.

    4. Checking Serial Data
    a. Verify the transmitter data rate and the receiver expected rate are the same.

    b. Measure lanes with high-impedance probe (differential probe, if possible); if characters appear incorrect, make sure lane differential traces are matched, the return path on the PCB is not interrupted, and devices are properly soldered on the PCB. CGS characters are easily recognizable on a high speed scope.

    c. Verify /K/ characters with high impedance probe. (If /K/ characters are correct, the Tx side of the link is working properly.

    If /K/ characters are not correct, the Tx device or the board lanes signal have an issue.

    d. Verify the transmitter CML differential voltage on the data lanes
    e. Verify the receiver CML differential voltage on the data lanes

    f. Verify that the configuration parameters M and L values match between the baseband processor and the transceiver, otherwise the data rates may not match.

    For example, M = 2 and L = 2 expect ½ the data rate over the serial interface as compared to the M = 2 and L = 1 case.

    g. Ensure the device clock is phase locked and at the correct frequency.