The platform we are using is ZC706+ADRV9026-MB/PCBZ (sub board), and the corresponding software version is 188.8.131.52。
We have made modifications to the FPFA project of ZC706+ADRV9009 and replaced the FPGA related code in ADRV9029 with the FPGA related code in ADRV9009 sdk.
And the polarity of SYNCOUT, SERDOUT, and SERDIN has been processed to ensure that there are no issues.
But during operation, in adi_ Board_ Adrv9025_ In JesdTxBrigup(), run ADI_ ADRV9025_ SERDES_ INIT, print 'error: SERDES: Lane is powered down'.
May I ask what is the cause of this problem?