How to control the internal switch which switches between the external ORX RF inputs in ADRV9025?

See below for our comments:

1.Yes, you can assign the GPIOs as required from the GUI/ stream settings. See highlighted in yellow where the GPIOs are used.

Ben68 said:

Should I pick GPIOs by myself and determine them as ORXx_TX_SEL & ORXx_TX_EN?

2. You don't need GPIOs. they can be defaulted to a fixed state through SPI as they are fixed.

Ben68 said:

Should I control them by GPIO signals and make FPGA output fixed 1/0? If not,can I just pull these GPIO up and down by Pull-up/down resistance? When I switch to RX Mode,will these ORx config for TX DPD affect the work of RX?

The internal cals like DPD, CLGC, etc are scheduled by DPD. No, the DPD works when the TX_EN is enabled.

3.

Ben68 said:

In 4 Transmitter/4 Receiver/4 Observation Receiver Input Use Case, I want to make ORX1 & ORX3 work at the same time,can I do so? and how if I can? ORX_CTRL_D does not mentioned,what should i do with ORX_CTRL_D?

No, at any point of time, the DPD works on one channel only.  In Dual channel 4 Pin mode, ORX_CTRL_D is used.

Thanks a lot! Your answer is really helpful.

I want to continue to ask about question 2, the 4 Transmitter/4 Receiver/4 Observation Receiver Input Use Case.My system will most likely work in this case.

1. According to my understanding and your answer, I think the Figure 70 has these 3 problems,and I marked my understanding with a red pen in the screenshot below, am I right？

2. In Figure 70 ORX USAGE has two stages, performing calculation on PAx and TXx calibration.I want to kown,what calculation it is performing on PA?Is it anlyzing the nonlinearity of PA and calculating DPD?After that, TX calibration use the previous PA calculation results for the DPD calibration of TX?As I indicated by the blue arrow in the picture above?

3. What about TX external calculation(external QEC & DC offset) for reducing the leakage of LO and strengthen mirror suppression by using ORX, does this fuction performed in the process in Figure 70?

1. Your understanding is correct on the Pin, ORX_CTRL_C, it was a typo in the block diagram in the latest UG whereas this was correctly mentioned in the previous version UG as shown below:

The understanding on when the calibrations run is not correct.

.

2. When ORX_CTRL_A is high and when ORX_CTRL_B/C are set to low, the ORX1 data goes to the FPGA through JESD and during this time, the internal calibrations such as LOL/ DPD can run on ORX3/4 paths. You can do any calculations in the FPGA as the ORX data is available to the FPGA

3. These are internal calibrations and will be run during the respective calibrations time.

Thanks！Your explanation helps a lot.

Where can I get the latest UG?I downloaded this version in the following page,but it is not the latest one.Thanks！

https://www.analog.com/en/products/adrv9026.htm

Unfortunately, the latest UG has the mistake and the Old UG is correct wrto the control Pin. I could not upload the previous revision UG here due to size restrictions. I would request you to go with the correction, ORX_CTRL_C instead of ORX2_TX_SEL.