ADRV9026 JESD204B Bring up

liehang said:

the SYNC signal has been unable to pull up

It seems JESD link is failing in CGS phase. Hope you are matching the framer and deframer configuration parameters.Have you tried with different usecases.Check the link integrity using PRBS testing. Please refer to this debugging document for more details  and  check if you are missing anything JESD_Debug .

We find through ILAS that it is indeed stuck in the cgs phase and the receiver does not receive K28.5 code.

Using the function 'adi_adrv9025_DfrmIlasMismatchGet' to compare the parameters we get the following result:

(Do I think it is because JESD204B link is not established?)

We are currently using the 51_NLS use case and haven't tried any of the other use cases yet (we will try them soon).

Thank you very much for your reply. We will try to use PRBS testing for checking the link intergrity and refer to the information you sent.

We have tried different usecases, but they always failed to complete the initialization.It was later discovered that because SYNCIN was not inverted, the change resulted in framer status = 0x0A, but deframer status was still 0x12. And we don't even see the sync signal pull up with vivado ILA.

We tested link integrity by using PRBS and the results also seem to show incomplete.

Could you tell me how to check such a problem?

Please check the below post if you are missing out any steps in the recommended sequence?

 RE: ADRV9026 Framer Link Set Up Procedure 

We used the usecase 51_NLS and masked the unneeded part. And we also masked the FPGA part. The other parts are in the order of the post you sent.

liehang said:

We tested link integrity by using PRBS and the results also seem to show incomplete

Have you tried adjusting the drive strength using pre-emphasis and equalization to pass the PRBS test?

Also try to send know user data sequence and receive the same at receiver.

Please refer to this post for more details. Reference post

No, you wont be able to change through GUI and we have an API to change the serializer configuration settings. See below. 

Thank you so much, I will have a try.

Hi, Ramarao.

We've tried, but we haven't got much information. The following image is obtained on ILA:

Among them:

state <= tx_sync_b & tx_sync_a & rx_sync_c & rx_sync_b & rx_sync_a & tx_reset_gt & tx_reset_done & rx_reset_done;

Do you have any good suggestions for finding and solving problems?