Is it possible to control ADRF5515 over ADRV9025's GPIOs?

Hi,

ADRF5515 control voltage thresholds are:

SWCTRL & PD: 0 - 0.7V low , 1.4V - Vdd high
BPA & BPB: 0 - 0.3V low , 1V - Vdd high

ADRV902x general purpose IOs are shared with their limits for logic low and high voltages. When supplied with 1.8V, logic low limit would be 0.45V and logic high limit would be 1.35V.

1) For BPA&BPB pins, 0.45V logic low limit does not stay with-in 0 to 0.3V but 1.35V is above 1V-Vdd range. You may consider using an external pull-down resistor with appropriate value to guarantee pulling down below 0.3V

2) For SWCTRL & PD pins, 0.45V logic is inside 0 - 0.7V logic low internal and it looks find. For the high side 1.35V is slightly below 1.4V threshold. You may consider an external pull-up to 1.8V with appropriate value to guarantee the logic high.

Hope this helps

In addition to my colleagues question and your answer I have the following inquiry;

Aside from the voltage levels, to control ADRF5515 precisely during TDD operation these outputs need to be synchronised with the with the transmit and receive duty cycles with respect to data. Since setting of these outputs are done through API with SPI instructions; is there deterministic latency on these outputs?

Is there a timing diagram that shows the instruction to output timing response?

Yes there is a deterministic latency, defined in the datasheet specification table.