ADRV9026 bring-up

Are you generating the resource files from the GUI?

Which Profile are you using? Is it 204B or 204C? Can you send us the full log?

Please check if the Dev clock, Sysref are fine? Also, please check if Dev clock in the initdata.c and the fed Dev clock are matching

Please follow the post for more details

 ADRV9026 Framer Link Set Up Procedure 

We are generating the source files from the GUI. Since we are using custom hardware, we are launching it in demo mode to create the profile.

The profile and log attached to this post are using the 51_nonLinkSharing profile with K changed from 32 to 8. The JESD standard being used is 204B.  I had to append .txt to the .profile file in order to attach it here.

According to the profile, Dev clock is 245.76 MHz and Sysref was manually calculated to be 7.68 MHz. We verified Sysref using an oscilloscope. Dev clock was verified using the FPGA since our oscilloscope can't measure it. The supplied Dev clock matches the Dev clock in initdata.c.

Our Initialization process is as follows:

• Enable on-board power supplies
• Configure clock generator
• Take Xilinx JESD cores out of reset
• Initialize the ADRV9026

We are running into the "Bootup Jesd setup error" before the initialization code even attempts to bring up the JESD data link. We're using the provided main.c in adrv9026-customerpkg-broad-market-release/Adi.Adrv9025.Api/src_broad_market/c_src/app/example with the FPGA specific code removed. We can provide the ADRV9026 initialization code if needed.

adrv9026_hal.txtGeneratedProfile.profile.txt

Apologies for the delay, we will get back to you ASAP.

• Check  Framer0 & Framer1 status by call API function adi_adrv9025_FramerStatusGet()
• Check  Deframer0 & Deframer1 status by call API function adi_adrv9025_DeframerStatusGet()
• What is the Sync signal status?
• Are you using single shot or continuous SYSREF?

Hi, 

we are trying to bring up ADRV9026 with intel S10 FPGA.We are facing the same issue

" Bootup Jesd setup error" in adi_adrv9025_CpuStartStatusCheck() . We are stuck in this from long time .Hoping for some help.

Thanks in advance

VK19

Did you try building the app example where in the complete Integration process is explained.

ez.analog.com/.../documents

You need to replace the HAL fucntions for your FPGA. I guess SPI verify is passing and able to load ARM binaries as well and the issue with JESD bring up? If so, then JESD bringup sequence is being missed.

DEVCLK and SYSREF are fine? Is your DEVCLK and  initdata.c DEVCLK same?

What is the Framer and deframer status?