Question on how to receive ORX data through JESD after DPD operation in ADRV9029

Justin.Jung said:

However, although I enabled it on the RXx_en pin, ORx Data is not coming in through JESD.

You are using a link sharing profile so the ORX data comes on JESD only when the TX is on.

Justin.Jung said:

I know that no ORX data is coming out through JESD during DPD operation.

Yes, but the other ORX side of the chip can get the JESD data.

See below:

When ORX_CTRL_A is high and based on CTRL_B and CTRL_C logics, the respective ORX data goes to the JESD and on the other ORX side of the chip, the DPD cal will run.

Justin.Jung said:

However, although I enabled it on the RXx_en pin, ORx Data is not coming in through JESD.

You are using a link sharing profile so the ORX data comes on JESD only when the TX is on.

Justin.Jung said:

I know that no ORX data is coming out through JESD during DPD operation.

Yes, but the other ORX side of the chip can get the JESD data.

See below:

When ORX_CTRL_A is high and based on CTRL_B and CTRL_C logics, the respective ORX data goes to the JESD and on the other ORX side of the chip, the DPD cal will run.

TXx_en is correct, not RXx_en. I wrote it wrong by mistake.

Currently, in 3pin mode, DPD from Tx1 to 4 is operating normally.

Can I know when the link sharing ORx data comes out through JESD after the ORx path is used by the DPD actuator? (Time to capture ORX in FPGA is limited, so please inquire.)

Additionally, when DPD is executed on ORx1,2, ORX data should appear on ORx3,4, but ORX data is not displayed through JESD.

In this regard, please let me know if there is anything I need to check or if there is any data needed to analyze this issue.

While the DPD is running on one side of the ORX, the other side of the ORX data will be available on the JESD.

Is the other side of the ORX data is available through your external path routing for the FPGA on the JESD?

Is your Use case has ORX enabled?

On my board I am using 51_LinkSharing.

I think it's an API setting problem. What data can we provide to confirm the problem? (code, etc.)

Please help.

thank you

Are you testing on a custom board or EVB?

If on EVB, Use Play button in ORX tab and check if ORX data is displayed in the FFT plot in the GUI.

What is your Tx-ORX mapping, are you using any GPIOs for external controls?

Have you generated the resource files like initdata.c and the binaries from the GUI after configuring the GPIO mapping. For eg, you need to map the GPIOs as per your requirement.

This is a custom board we made, and the current DPD is running normally.

We will send you the configuration file created in the GUI as an attachment.
UC51-LS is used, and RF LO is being modified directly in the generated file.

Please help.

thank you

adrv_51LinkSharing.zip

While the DPD is running on one side of the ORX, please check if the data is available on the ORX side which will go to the FPGA over JESD.

Are you using 4 Tx/4 Rx/4 ORx Input Use Case as described in Page 115 of the UG? Can you check/ monitor if ORX_CTRL_A is pulled high, this is mandatory for the data to go to FPGA over JESD.

Ramarao said:

Can you check/ monitor if ORX_CTRL_A is pulled high, this is mandatory for the data to go to FPGA over JESD.

If so, is it correct to keep ORX_CTRL_A as "Low" in the UL (RX) section?

please answer about my question.

No, you can still keep the CTRL_A high even during RX duration.

We are using UC51-Link sharing.

If so, is there no effect on data in JESD RX/ORx lane?

Please advise.

During the TX duration, you get ORX data and during RX duration, you get RX data on the JESD. There should not be any problem.