When ORx selection is SPI mode, can DPD work on all 4 ports?

Whats your TX to ORX mapping, is it One to One?

Justin.Jung said:

However, when DPD is enabled for Port1 (Tx1, ORx1) and Port3 (Tx3, Orx3) sequentially, only Port3 that has been controlled last operates DPD.

How you are controlling?

If TX1 is connected to ORX1, TX2 to ORX2, TX3 to ORX3 and TX4 to ORX4 and if ORX_CTRL_A is low, the DPD will run on all the 4 channels and when to run the DPD is decided by ARM inside the chip.

if 4 Transmitter/4 Receiver/4 Observation Receiver Configuration, is it possible to control in TDD in SPI mode?

Also, 3 Pin mode is not directly related to DPD, is it the necessary function to output ORX data through JESD?

Yes,It is possible to control Tx/Rx/Orx through both SPI and pin mode in TDD mode.But it is recommended to use Pin mode in TDD mode for critical timing alignment.

Justin.Jung said:

is it the necessary function to output ORX data through JESD?

It is not required to output Orx data through JESD to enable onchip DPD feature.But you can use this Orx data through JESD to perform your own DPD mechanism and also to analyse the data being transmitted in Tx channel.

Thank you for your response.

What is the relationship between pin mode and DPD?

According to your mention, you recommended pin mode for critical timing alignment in TDD mode.
However, doesn't the ARM controlling DPD determine the timing of DPD execution by TX_EN in TDD?

I understood PIN MODE as a control signal that allows selecting the timing to send ORX signal to JESD.

FYI, The Chip does not support mixed mode (TX/RX in SPI mode & ORX in PIN mode OR Vice Versa). All the TX/RX/ORX channels have to be either in SPI mode or PIN mode.

In FDD mode, you would need to change the TX to ORX mapping as needed if not in One to One mode. In TDD mode, you need to let the ARM know which channels are enabled depending on the Tx/RX/ORX Use Cases based on Tx-ORX mapping mode and based on that, the internal tracking cals like LOL, DPD, etc will be running.

If you need the ORX data to be sent over JESD to the FPGA, you would need the control signal ORX_CTRL_A signal to be high.

I use it with 4T4R4ORX configuration and use TDD. Already the mapping between Tx and ORx is 1:1.

So I don't think "pin mode" is strictly necessary. Is that correct?

Also, what does "critical timing alignment" mean in the phrase quoted below?

Vinod_Mekala said:

But it is recommended to use Pin mode in TDD mode for critical timing alignment.

Justin.Jung said:

I don't think "pin mode" is strictly necessary

You can use SPI mode as well. TDD system requires proper timing alignment between Tx and Rx as per the TDD timing. Pin mode offers low latency than SPI mode, so PIN mode is preferrable for TDD systems.