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ADRV9026 initCal TXBBF error

Hello,

Sometimes, during init calibration I run into this:

CpuCmdStatusWait() failed due to thrown CPU error. Is device in correct state for calling command?
ADRV9025 CPU Command Error
TXBBF:Calibration results are invalid

It happens around 5% of my runs, and then ARM is not accessible any more, a reset and a new initialization is required.

Consider we have a multi-adrv9026 equipped board and the problem is randomly affecting one of the 16 chips, not always the same.

Any suggestion for a further investigation ?

BR

Pietro

Parents
  • If you are enabling only a single ADRV9025, how consitent is the error?

    Two things to check,

    - Check the TX Port RF impedance matching of the device is good for the bandwidth of LO +/- Sampling rate/2 of the profile.

    - Please check whether any of the power suppply voltage is droping on the board because of in-rush current requirement.

  • Hello,
    Board Rf port impedance is correct and we see no power faults.

    we still have errors by disabling all chips but one, statistics are very hard to get but I would say in 40 startups we have the error.

    I disabled ADI_ADRV9025_TX_BB_FILTER inside calMask and the error went away, I experienced over 300 startup without problems on all 16 chip we assembled on board;
    that means, in my opinion, it is not a software problem but it is Hw related.

    In your example code initdata.c (coming with api version 5.1.0.21 source code) I see a couple of main differenced from my one :

    .lo1PllFreq_Hz = 3500000000U,
    .lo2PllFreq_Hz = 3600000000U,
    .auxPllFreq_Hz = 0,

    .calMask = 866303 // (0x37FF)

    while I have, (we got initdata.c from profile 50)

           3000000000U, // lo1PllFreq_Hz
           0U, // lo2PllFreq_Hz
           0U // auxPllFreq_Hz

           0x40D7FFF, // was 0xD27FF THEN we added TX_QEC, LOOPBACK_RX_QEC, RX_GAIN_DELAY, RX_GAIN_PHASE, TX_LO_LEAKAGE_EXTERNAL

    Of course ADI_ADRV9025_TX_LO_LEAKAGE_EXTERNAL is run after all internal cals are over, and with PA on, as described in user manual

    1) we are not using LO2 pll
    2) we start with different LO1 frequency
    3) we run more calibrations than the example does

    then the questions:

    - in which way is TX_BB_FILTER calibration failing ? can I read some status register to have more details when the error occurs ?
    - can we be full operative without running it ?
    - does TX_BB_FILTER calib conflict with other calibrations we run ?

    BR

    Pietro

Reply
  • Hello,
    Board Rf port impedance is correct and we see no power faults.

    we still have errors by disabling all chips but one, statistics are very hard to get but I would say in 40 startups we have the error.

    I disabled ADI_ADRV9025_TX_BB_FILTER inside calMask and the error went away, I experienced over 300 startup without problems on all 16 chip we assembled on board;
    that means, in my opinion, it is not a software problem but it is Hw related.

    In your example code initdata.c (coming with api version 5.1.0.21 source code) I see a couple of main differenced from my one :

    .lo1PllFreq_Hz = 3500000000U,
    .lo2PllFreq_Hz = 3600000000U,
    .auxPllFreq_Hz = 0,

    .calMask = 866303 // (0x37FF)

    while I have, (we got initdata.c from profile 50)

           3000000000U, // lo1PllFreq_Hz
           0U, // lo2PllFreq_Hz
           0U // auxPllFreq_Hz

           0x40D7FFF, // was 0xD27FF THEN we added TX_QEC, LOOPBACK_RX_QEC, RX_GAIN_DELAY, RX_GAIN_PHASE, TX_LO_LEAKAGE_EXTERNAL

    Of course ADI_ADRV9025_TX_LO_LEAKAGE_EXTERNAL is run after all internal cals are over, and with PA on, as described in user manual

    1) we are not using LO2 pll
    2) we start with different LO1 frequency
    3) we run more calibrations than the example does

    then the questions:

    - in which way is TX_BB_FILTER calibration failing ? can I read some status register to have more details when the error occurs ?
    - can we be full operative without running it ?
    - does TX_BB_FILTER calib conflict with other calibrations we run ?

    BR

    Pietro

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