ADRV9025 register map specification document

Register Map document is not available for ADRV9025 device.

We provide only the API source code for ADRV9025 Transceiver which can be used to configure the device.

For example application, please refer to Adi.Adrv9025.Api\src\c_src\app\example folder.

Hi PVALAVAN,

Thanks for the reply.

While we are bringing up the JESD 204B link, performing phy PRBS test,  below is the observation and not able to make the linkup.

1.At baseband framer is passing from CGS, ILAs, USER_DATA state but at the ADRV9025 deframer side, we are not getting proper deframer status(i.e adrv deframer status shows always 0x10).

2.ADRV deframer status sysref bit is not getting set. read the 0x6A88 register over SPI in status check api, but shows 0x10

3.ADRV deframer status sync bit is also not getting set. but we are receiving sync pulse at the baseband framer after that only it is entering into CGS state.

4.we are not able to receive /K28.5/ characters from the ADRV9025 framer so bcoz of this baseband deframer is not generating the syncb pulse.

5.and framer status we are getting always zero.

6.what is the use of external sysref and how to enable it. Using the api adi_adrv9025_FramerSysrefCtrlSet() we are enabling sysref for framer at address: ADRV9025_BF_JTX_LINK0= 0x6E00. In the document externalSysref  attribute is mentioned in the structure adi_adrv9025_FrmCfg, but source code is not having externalSysref attribute. which register to use to set externalSysref.

7.How the lane inverse polarity will impact and where it can impact?

8.Using the GUI EVB tool, we are generating initdata.c file and resources. But, if we use resources  firmware bins on the adrv9025, initialization is failing. So, we are using the resources provided along with the ADI SDK package which is working fine for the initialization. Do we need to use the firmware generated from the GUI tool only?.

Could you please help in this regard in bringing-up the jesd.

Thanks and Regards

srinivasa

Please refer to the below post for the JESD204 link bring up procedure.

https://ez.analog.com/wide-band-rf-transceivers/design-support-adrv9026/f/q-a/120972/adrv9026-framer-link-set-up-procedure

ADRV9025 said:

How the lane inverse polarity will impact and where it can impact?

Lane inverse polrity option is provided for routing (Layout) flexibility.

If polatiry mismatch is there the link will not come up and will have stability issues. (Link drops in-between)

ADRV9025 said:

8.Using the GUI EVB tool, we are generating initdata.c file and resources. But, if we use resources  firmware bins on the adrv9025, initialization is failing. So, we are using the resources provided along with the ADI SDK package which is working fine for the initialization. Do we need to use the firmware generated from the GUI tool only?.

It is not recommended to mix and match Initdata.c files and resources files from different software release version.

If you are facing any issue with initialization please share the log files.

Hi PVALAVAN,

Thanks for the reply.

1. Is there any way to dump the Tx/Rx Channel data at adrv9025 to cross check the data integrity. I saw below register addresses in file adrv9025_reg_addr_macros.h. I tried  to read the  Tx channel data  at address 0x1E00 over spi adi_adrv9025_SpiByteRead(adrv9025Device, 0x1E00, &tmp_data).

#define ADRV9025_ADDR_CH0_RX 0x1200
#define ADRV9025_ADDR_CH1_RX 0x1400
#define ADRV9025_ADDR_CH2_RX 0x1600
#define ADRV9025_ADDR_CH3_RX 0x1800

#define ADRV9025_ADDR_CH0_TX 0x1E00
#define ADRV9025_ADDR_CH1_TX 0x2000
#define ADRV9025_ADDR_CH2_TX 0x2200
#define ADRV9025_ADDR_CH3_TX 0x2400

Could you please let us know how to dump the Tx/Rx channel data at ADRV9025.

Thanks and Regards

srinivasa

There no provision capture/dump the actual data inside ADRV9025 device.

We have two differrent loopback method to debug the JESD204B interface.

1) Digital loopback.

 User can send known pattern from FPGA to ADRV9025 Deframer and do loopback to ADRV9025  Framer and capture the same data back at your FPGA. Please find the attached ironpython script to enable the digital loopback on ADRV9025.

2) RxtoTxLoopback enable

Digital_loopback_Jrx_Jtx_adrv902x.zipADRV9025_LoopRxDataToTx_Enableset.zip

Hi PVALAVAN,

we have implemented the jesd bring up sequence as per the link and ADRV custormer package from portal, except FPGA api at ADRV side. FPGA device instance we have not created at ADRV side. https://ez.analog.com/wide-band-rf-transceivers/design-support-adrv9026/f/q-a/120972/adrv9026-framer-link-set-up-procedure. 

1. We are getting the correct deframer status (0x87) but on the spectrum Analyzer, we are not able to see any LO2 frequency.

2. We tried with digital loopback writing reg 0x6689 data 0xD5. with this on the RX path, we are getting constant data, but when we are writing reg 0x6689  with data 0x29,  at that time some random data is coming  on Rx channel to FPGA, but not as expected what we are sending  incremental counter data at TX. Not sure TX->RX loopback is happening. could you please brief this 0x6689 register bits?

3. is there any GPIO in ADRV9025 through which we can send some input to the FPGA from adrv?.

4. We are generating initdata.c files using ADRV Transceiver Evaluation software, with that resources stream_image binary, ADRV initialization is failing while loading the stream image. Do we need to use the generated firmware(arm & stream) on a custom board?.Along with custom board we received Firmware(arm&stream image). If we change this firmware and update with the tool generated firmware we are observing ADRV initialization failure. Question is if we change the configuration(initdata.c) on the custom board do we need to change the Arm and Stream image Firmware?. 

JESD bringup logs:

=====================================

adi_adrv9025_PostMcsInit
RSYS: adi_adrv9025_RxTxEnableSet rxChannelMask=0xf txChannelMask=0x0
RSYS: adrv9025_TxEnableSet=0
RSYS: adi_adrv9025_RxTxEnableSet rxChannelMask=0x0 txChannelMask=0x0
RSYS: adrv9025_TxEnableSet=0
RSYS:adrv9025_RadioctrlInit
pllFreqLo2 900000000
JESD204 link bring up rxLinkSelect:0x1 txLinkSelect:0x1
RSYS:Mask All Deframer Sysref
RSYS:Mask all Framer Sysref set
JesdRxBringup link:0x1
RSYS:Mask all Framer Sysref set
RSYS:Mask all Framer Sysref set
framer Status outside RxBringup: 0x0a framerSyncNeCount 0x1 qbfStateStatus 0xd syncNSel 0x0.
RSYS: JesdTxBringup link:0x1
RSYS:Mask All Deframer Sysref
RSYS:Mask All Deframer Sysref
Get JESD Deframer status outside JesdTxBringup
RSYS:DeframerStauts Get baseAddr:0x6a00
RSYS:ADRV9025_BF_JRX_LINK0:0x6a00
Deframer SyncB:0x1
RSYS:drv9025_JrxLinkJrxTplSysrefRcvdBfGet bfValue=0x1
RSYS:Deframer SysrefRecvd:0x1
Deframer Status 0x87
RSYS: adrv9025LinkStatus =1 txLinkSel=1
RSYS: adi_adrv9025_RxTxEnableSet rxChannelMask=0xf txChannelMask=0xf
RSYS: adrv9025_TxEnableSet=15
framer Status outside RxBringup: 0x0a framerSyncNeCount 0x1 qbfStateStatus 0xd syncNSel 0x0.
Get JESD Deframer status in JesdTxBringup
RSYS:DeframerStauts Get baseAddr:0x6a00
RSYS:ADRV9025_BF_JRX_LINK0:0x6a00
Deframer SyncB:0x1
RSYS:drv9025_JrxLinkJrxTplSysrefRcvdBfGet bfValue=0x1
RSYS:Deframer SysrefRecvd:0x1
Deframer Status 0x87