ADRV9026 Tx Output Spectrum Abnormal Debug Hint

The user can refer to the " TRANSMITTER OVERVIEW AND PATH CONTROL” & “TRANSMITTER (DAC) DATAPATH” section in the ADRV9026 user guide to know the detailed working theory of ADRV9026 Tx path. If user find some issues related to Tx output spectrum , they can follow below instructions to identify the root cause:

1. The user can call the API function adi_adrv9025_TxTestToneSet to enable the internal TXNCO as the test tone . By this way the user can check the Tx output spectrum abnormal caused by the JESD link interface or just Tx data path after JESD interface block;
2. The user can loopback the Tx de-framer0 output to framer0 input by set register 0x6689[D5] as 1 to check if the Tx JESD work correctly or not . Take an example. If the Tx1 output signal is 5MHz offset -10dBFs CW tone. When 0x6689[D5] bit is enabled. The Rx1 will receive the Tx1 base band signal.
3.If the item1 & item2 show the JESD interface work abnormal , The user can debug further as below :
    A. Readback the registers 0x6B2B, 0x6B2C, 0x6B2D, 0x6B2E to check the 204C link status per lane. For a good case, a value of 0x6 is returned for the active lanes. The user can refer to the section ‘CHECKING JESD204C LINK STATUS’ in ADRV9026 user guide to understand the meaning of the other values returned from these registers.
    B. If the JESD204C link status is correct. The user can refer to the “Reading Back the Buffer Depths for Each Deframer Lanes” section in ADRV9026 user guide to read back the buffer depth and know maximum buffer depth under different configuration . When the reading back buffer depth is too close to the zero or max buffer depth. it can lead to the write and read pointers being too close and therefore can result in data corruption. When JESD parameter E>2. The size of each elastic buffer is 512 octets which limit the max buffer depth as 64. The user need to select an LEMC offset value giving buffer depths as close as possible to the center of the linear part of the buffer depth which is 32. Refer to the section “Selecting the Optimal LEMC Offset for a System in JESD204C Mode When E > 2” in the ADRV9026 user guide to sweep the LMFC offset and find the optimal setting.

    C.If the reading back value show the 204C link status is in wrong state. The user need to check the JESD204C setup procedure and some items as below:
        a) The user can refer to ADRV9026 JESD204C Framer/Deframer SYSREF status page on the Engineer Zone to check the de-framer SYSREF status.
        b) Read back register 0x6847[D0] for JESD PLL lock status. When JESD PLL lock, The 0x6847[D0] will be set high. The user can use GPINT1 or GPINT2 interrupt pin to monitor the JESD PLL lock status.
        c) Check the JESD204C configuration to make sure each side parameter setting matching with each other and correct;
        d) Run PRBS test to check the hardware integrity;

4.If the item1 & item2 show the JESD interface work correctly , The user can debug further as below :
    A. Call API function adi_adrv9025_PllStatusGet to get CLKPLL/RFLO1/RFLO2 PLL lock status. The user can use GPINT1 or GPINT2 interrupt pin to monitor these PLL lock status or call API function adi_adrv9025_GpIntStatusGet to monitor the GP interrupt status;
    B. Read back the register 0x1E2D,0x202D, 0x222D, 0x242D to check the Tx filter overflow status per Tx path. When the chip work normally . These register value read back should be zero. The user need to write the register with any value first and make sure the register is updated then read back. Below is the example on ADI EVB board is to read back the Tx1 path filter overflow status:
        #Tx1 path digital filter overflow status reading back
        spiWrite(0x1E2D,0xFF)
        spiRead(0x1E2D)
    C. Do the SPI register dump from 0x11C to 0x127 to get the LDO status. It is better to provide these registers dump with bad case vs good case;On the ADI EVB board , The reading back register value 0x11C ~0x127 list as below for reference:

    D. If possible , The user can provide the chip whole SPI registers dump with bad case vs good case;
ADI recommends the user to refer to the ADRV9026 FAQ page on the Engineer Zone to find the information that the user needs to provide to help speed resolution of any issues.